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authorDerek Foreman <derekf@osg.samsung.com>2016-04-19 13:42:20 -0500
committerMike Blumenkrantz <zmike@osg.samsung.com>2016-04-19 15:11:10 -0400
commitbaad0d50dbb64791984d2328a85a7592b24ea295 (patch)
treee556234cce8e147cd43c908ff9272172fd49dc5a /src/static_libs/libdrm
parent0d684d4559c6cd4e8195b3334ab07d3631a64887 (diff)
static_libs: Add libdrm headers (for wayland_shm)
wayland_shm's dmabuf implementation needs acess to libdrm headers for doing GPU specific memory allocations. We search for these libraries at runtime with dlopen, so we don't need to find them at build time, however certain struct definitions and defines are still required.
Diffstat (limited to 'src/static_libs/libdrm')
-rw-r--r--src/static_libs/libdrm/LICENSE17
-rw-r--r--src/static_libs/libdrm/drm.h867
-rw-r--r--src/static_libs/libdrm/drm_fourcc.h223
-rw-r--r--src/static_libs/libdrm/drm_mode.h556
-rw-r--r--src/static_libs/libdrm/i915_drm.h1146
-rw-r--r--src/static_libs/libdrm/intel_bufmgr.h321
6 files changed, 3130 insertions, 0 deletions
diff --git a/src/static_libs/libdrm/LICENSE b/src/static_libs/libdrm/LICENSE
new file mode 100644
index 0000000000..680e275eed
--- /dev/null
+++ b/src/static_libs/libdrm/LICENSE
@@ -0,0 +1,17 @@
1Permission is hereby granted, free of charge, to any person obtaining a
2copy of this software and associated documentation files (the "Software"),
3to deal in the Software without restriction, including without limitation
4the rights to use, copy, modify, merge, publish, distribute, sublicense,
5and/or sell copies of the Software, and to permit persons to whom the
6Software is furnished to do so, subject to the following conditions:
7
8The above copyright notice and this permission notice shall be included in
9all copies or substantial portions of the Software.
10
11THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
12IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
13FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
14AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
15LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
16FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
17IN THE SOFTWARE.
diff --git a/src/static_libs/libdrm/drm.h b/src/static_libs/libdrm/drm.h
new file mode 100644
index 0000000000..a950b580cd
--- /dev/null
+++ b/src/static_libs/libdrm/drm.h
@@ -0,0 +1,867 @@
1/**
2 * \file drm.h
3 * Header for the Direct Rendering Manager
4 *
5 * \author Rickard E. (Rik) Faith <faith@valinux.com>
6 *
7 * \par Acknowledgments:
8 * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg.
9 */
10
11/*
12 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
13 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
14 * All rights reserved.
15 *
16 * Permission is hereby granted, free of charge, to any person obtaining a
17 * copy of this software and associated documentation files (the "Software"),
18 * to deal in the Software without restriction, including without limitation
19 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
20 * and/or sell copies of the Software, and to permit persons to whom the
21 * Software is furnished to do so, subject to the following conditions:
22 *
23 * The above copyright notice and this permission notice (including the next
24 * paragraph) shall be included in all copies or substantial portions of the
25 * Software.
26 *
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
28 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
29 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
30 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
31 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
32 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
33 * OTHER DEALINGS IN THE SOFTWARE.
34 */
35
36#ifndef _DRM_H_
37#define _DRM_H_
38
39#if defined(__linux__)
40
41#include <linux/types.h>
42#include <asm/ioctl.h>
43typedef unsigned int drm_handle_t;
44
45#else /* One of the BSDs */
46
47#include <sys/ioccom.h>
48#include <sys/types.h>
49typedef int8_t __s8;
50typedef uint8_t __u8;
51typedef int16_t __s16;
52typedef uint16_t __u16;
53typedef int32_t __s32;
54typedef uint32_t __u32;
55typedef int64_t __s64;
56typedef uint64_t __u64;
57typedef unsigned long drm_handle_t;
58
59#endif
60
61#define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */
62#define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */
63#define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */
64#define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */
65
66#define _DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */
67#define _DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */
68#define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD)
69#define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT)
70#define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT))
71
72typedef unsigned int drm_context_t;
73typedef unsigned int drm_drawable_t;
74typedef unsigned int drm_magic_t;
75
76/**
77 * Cliprect.
78 *
79 * \warning: If you change this structure, make sure you change
80 * XF86DRIClipRectRec in the server as well
81 *
82 * \note KW: Actually it's illegal to change either for
83 * backwards-compatibility reasons.
84 */
85struct drm_clip_rect {
86 unsigned short x1;
87 unsigned short y1;
88 unsigned short x2;
89 unsigned short y2;
90};
91
92/**
93 * Drawable information.
94 */
95struct drm_drawable_info {
96 unsigned int num_rects;
97 struct drm_clip_rect *rects;
98};
99
100/**
101 * Texture region,
102 */
103struct drm_tex_region {
104 unsigned char next;
105 unsigned char prev;
106 unsigned char in_use;
107 unsigned char padding;
108 unsigned int age;
109};
110
111/**
112 * Hardware lock.
113 *
114 * The lock structure is a simple cache-line aligned integer. To avoid
115 * processor bus contention on a multiprocessor system, there should not be any
116 * other data stored in the same cache line.
117 */
118struct drm_hw_lock {
119 __volatile__ unsigned int lock; /**< lock variable */
120 char padding[60]; /**< Pad to cache line */
121};
122
123/**
124 * DRM_IOCTL_VERSION ioctl argument type.
125 *
126 * \sa drmGetVersion().
127 */
128struct drm_version {
129 int version_major; /**< Major version */
130 int version_minor; /**< Minor version */
131 int version_patchlevel; /**< Patch level */
132 size_t name_len; /**< Length of name buffer */
133 char *name; /**< Name of driver */
134 size_t date_len; /**< Length of date buffer */
135 char *date; /**< User-space buffer to hold date */
136 size_t desc_len; /**< Length of desc buffer */
137 char *desc; /**< User-space buffer to hold desc */
138};
139
140/**
141 * DRM_IOCTL_GET_UNIQUE ioctl argument type.
142 *
143 * \sa drmGetBusid() and drmSetBusId().
144 */
145struct drm_unique {
146 size_t unique_len; /**< Length of unique */
147 char *unique; /**< Unique name for driver instantiation */
148};
149
150struct drm_list {
151 int count; /**< Length of user-space structures */
152 struct drm_version *version;
153};
154
155struct drm_block {
156 int unused;
157};
158
159/**
160 * DRM_IOCTL_CONTROL ioctl argument type.
161 *
162 * \sa drmCtlInstHandler() and drmCtlUninstHandler().
163 */
164struct drm_control {
165 enum {
166 DRM_ADD_COMMAND,
167 DRM_RM_COMMAND,
168 DRM_INST_HANDLER,
169 DRM_UNINST_HANDLER
170 } func;
171 int irq;
172};
173
174/**
175 * Type of memory to map.
176 */
177enum drm_map_type {
178 _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */
179 _DRM_REGISTERS = 1, /**< no caching, no core dump */
180 _DRM_SHM = 2, /**< shared, cached */
181 _DRM_AGP = 3, /**< AGP/GART */
182 _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */
183 _DRM_CONSISTENT = 5, /**< Consistent memory for PCI DMA */
184 _DRM_GEM = 6 /**< GEM object */
185};
186
187/**
188 * Memory mapping flags.
189 */
190enum drm_map_flags {
191 _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */
192 _DRM_READ_ONLY = 0x02,
193 _DRM_LOCKED = 0x04, /**< shared, cached, locked */
194 _DRM_KERNEL = 0x08, /**< kernel requires access */
195 _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */
196 _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */
197 _DRM_REMOVABLE = 0x40, /**< Removable mapping */
198 _DRM_DRIVER = 0x80 /**< Managed by driver */
199};
200
201struct drm_ctx_priv_map {
202 unsigned int ctx_id; /**< Context requesting private mapping */
203 void *handle; /**< Handle of map */
204};
205
206/**
207 * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls
208 * argument type.
209 *
210 * \sa drmAddMap().
211 */
212struct drm_map {
213 unsigned long offset; /**< Requested physical address (0 for SAREA)*/
214 unsigned long size; /**< Requested physical size (bytes) */
215 enum drm_map_type type; /**< Type of memory to map */
216 enum drm_map_flags flags; /**< Flags */
217 void *handle; /**< User-space: "Handle" to pass to mmap() */
218 /**< Kernel-space: kernel-virtual address */
219 int mtrr; /**< MTRR slot used */
220 /* Private data */
221};
222
223/**
224 * DRM_IOCTL_GET_CLIENT ioctl argument type.
225 */
226struct drm_client {
227 int idx; /**< Which client desired? */
228 int auth; /**< Is client authenticated? */
229 unsigned long pid; /**< Process ID */
230 unsigned long uid; /**< User ID */
231 unsigned long magic; /**< Magic */
232 unsigned long iocs; /**< Ioctl count */
233};
234
235enum drm_stat_type {
236 _DRM_STAT_LOCK,
237 _DRM_STAT_OPENS,
238 _DRM_STAT_CLOSES,
239 _DRM_STAT_IOCTLS,
240 _DRM_STAT_LOCKS,
241 _DRM_STAT_UNLOCKS,
242 _DRM_STAT_VALUE, /**< Generic value */
243 _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */
244 _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */
245
246 _DRM_STAT_IRQ, /**< IRQ */
247 _DRM_STAT_PRIMARY, /**< Primary DMA bytes */
248 _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */
249 _DRM_STAT_DMA, /**< DMA */
250 _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */
251 _DRM_STAT_MISSED /**< Missed DMA opportunity */
252 /* Add to the *END* of the list */
253};
254
255/**
256 * DRM_IOCTL_GET_STATS ioctl argument type.
257 */
258struct drm_stats {
259 unsigned long count;
260 struct {
261 unsigned long value;
262 enum drm_stat_type type;
263 } data[15];
264};
265
266/**
267 * Hardware locking flags.
268 */
269enum drm_lock_flags {
270 _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */
271 _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */
272 _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */
273 _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */
274 /* These *HALT* flags aren't supported yet
275 -- they will be used to support the
276 full-screen DGA-like mode. */
277 _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */
278 _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */
279};
280
281/**
282 * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type.
283 *
284 * \sa drmGetLock() and drmUnlock().
285 */
286struct drm_lock {
287 int context;
288 enum drm_lock_flags flags;
289};
290
291/**
292 * DMA flags
293 *
294 * \warning
295 * These values \e must match xf86drm.h.
296 *
297 * \sa drm_dma.
298 */
299enum drm_dma_flags {
300 /* Flags for DMA buffer dispatch */
301 _DRM_DMA_BLOCK = 0x01, /**<
302 * Block until buffer dispatched.
303 *
304 * \note The buffer may not yet have
305 * been processed by the hardware --
306 * getting a hardware lock with the
307 * hardware quiescent will ensure
308 * that the buffer has been
309 * processed.
310 */
311 _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */
312 _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */
313
314 /* Flags for DMA buffer request */
315 _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */
316 _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */
317 _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */
318};
319
320/**
321 * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type.
322 *
323 * \sa drmAddBufs().
324 */
325struct drm_buf_desc {
326 int count; /**< Number of buffers of this size */
327 int size; /**< Size in bytes */
328 int low_mark; /**< Low water mark */
329 int high_mark; /**< High water mark */
330 enum {
331 _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */
332 _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */
333 _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */
334 _DRM_FB_BUFFER = 0x08, /**< Buffer is in frame buffer */
335 _DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */
336 } flags;
337 unsigned long agp_start; /**<
338 * Start address of where the AGP buffers are
339 * in the AGP aperture
340 */
341};
342
343/**
344 * DRM_IOCTL_INFO_BUFS ioctl argument type.
345 */
346struct drm_buf_info {
347 int count; /**< Entries in list */
348 struct drm_buf_desc *list;
349};
350
351/**
352 * DRM_IOCTL_FREE_BUFS ioctl argument type.
353 */
354struct drm_buf_free {
355 int count;
356 int *list;
357};
358
359/**
360 * Buffer information
361 *
362 * \sa drm_buf_map.
363 */
364struct drm_buf_pub {
365 int idx; /**< Index into the master buffer list */
366 int total; /**< Buffer size */
367 int used; /**< Amount of buffer in use (for DMA) */
368 void *address; /**< Address of buffer */
369};
370
371/**
372 * DRM_IOCTL_MAP_BUFS ioctl argument type.
373 */
374struct drm_buf_map {
375 int count; /**< Length of the buffer list */
376#ifdef __cplusplus
377 void *virt;
378#else
379 void *virtual; /**< Mmap'd area in user-virtual */
380#endif
381 struct drm_buf_pub *list; /**< Buffer information */
382};
383
384/**
385 * DRM_IOCTL_DMA ioctl argument type.
386 *
387 * Indices here refer to the offset into the buffer list in drm_buf_get.
388 *
389 * \sa drmDMA().
390 */
391struct drm_dma {
392 int context; /**< Context handle */
393 int send_count; /**< Number of buffers to send */
394 int *send_indices; /**< List of handles to buffers */
395 int *send_sizes; /**< Lengths of data to send */
396 enum drm_dma_flags flags; /**< Flags */
397 int request_count; /**< Number of buffers requested */
398 int request_size; /**< Desired size for buffers */
399 int *request_indices; /**< Buffer information */
400 int *request_sizes;
401 int granted_count; /**< Number of buffers granted */
402};
403
404enum drm_ctx_flags {
405 _DRM_CONTEXT_PRESERVED = 0x01,
406 _DRM_CONTEXT_2DONLY = 0x02
407};
408
409/**
410 * DRM_IOCTL_ADD_CTX ioctl argument type.
411 *
412 * \sa drmCreateContext() and drmDestroyContext().
413 */
414struct drm_ctx {
415 drm_context_t handle;
416 enum drm_ctx_flags flags;
417};
418
419/**
420 * DRM_IOCTL_RES_CTX ioctl argument type.
421 */
422struct drm_ctx_res {
423 int count;
424 struct drm_ctx *contexts;
425};
426
427/**
428 * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type.
429 */
430struct drm_draw {
431 drm_drawable_t handle;
432};
433
434/**
435 * DRM_IOCTL_UPDATE_DRAW ioctl argument type.
436 */
437typedef enum {
438 DRM_DRAWABLE_CLIPRECTS
439} drm_drawable_info_type_t;
440
441struct drm_update_draw {
442 drm_drawable_t handle;
443 unsigned int type;
444 unsigned int num;
445 unsigned long long data;
446};
447
448/**
449 * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type.
450 */
451struct drm_auth {
452 drm_magic_t magic;
453};
454
455/**
456 * DRM_IOCTL_IRQ_BUSID ioctl argument type.
457 *
458 * \sa drmGetInterruptFromBusID().
459 */
460struct drm_irq_busid {
461 int irq; /**< IRQ number */
462 int busnum; /**< bus number */
463 int devnum; /**< device number */
464 int funcnum; /**< function number */
465};
466
467enum drm_vblank_seq_type {
468 _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */
469 _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */
470 _DRM_VBLANK_EVENT = 0x4000000, /**< Send event instead of blocking */
471 _DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */
472 _DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */
473 _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */
474 _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking, unsupported */
475};
476
477#define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE)
478#define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_EVENT | _DRM_VBLANK_SIGNAL | \
479 _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS)
480
481struct drm_wait_vblank_request {
482 enum drm_vblank_seq_type type;
483 unsigned int sequence;
484 unsigned long signal;
485};
486
487struct drm_wait_vblank_reply {
488 enum drm_vblank_seq_type type;
489 unsigned int sequence;
490 long tval_sec;
491 long tval_usec;
492};
493
494/**
495 * DRM_IOCTL_WAIT_VBLANK ioctl argument type.
496 *
497 * \sa drmWaitVBlank().
498 */
499union drm_wait_vblank {
500 struct drm_wait_vblank_request request;
501 struct drm_wait_vblank_reply reply;
502};
503
504#define _DRM_PRE_MODESET 1
505#define _DRM_POST_MODESET 2
506
507/**
508 * DRM_IOCTL_MODESET_CTL ioctl argument type
509 *
510 * \sa drmModesetCtl().
511 */
512struct drm_modeset_ctl {
513 __u32 crtc;
514 __u32 cmd;
515};
516
517/**
518 * DRM_IOCTL_AGP_ENABLE ioctl argument type.
519 *
520 * \sa drmAgpEnable().
521 */
522struct drm_agp_mode {
523 unsigned long mode; /**< AGP mode */
524};
525
526/**
527 * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type.
528 *
529 * \sa drmAgpAlloc() and drmAgpFree().
530 */
531struct drm_agp_buffer {
532 unsigned long size; /**< In bytes -- will round to page boundary */
533 unsigned long handle; /**< Used for binding / unbinding */
534 unsigned long type; /**< Type of memory to allocate */
535 unsigned long physical; /**< Physical used by i810 */
536};
537
538/**
539 * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type.
540 *
541 * \sa drmAgpBind() and drmAgpUnbind().
542 */
543struct drm_agp_binding {
544 unsigned long handle; /**< From drm_agp_buffer */
545 unsigned long offset; /**< In bytes -- will round to page boundary */
546};
547
548/**
549 * DRM_IOCTL_AGP_INFO ioctl argument type.
550 *
551 * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(),
552 * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(),
553 * drmAgpVendorId() and drmAgpDeviceId().
554 */
555struct drm_agp_info {
556 int agp_version_major;
557 int agp_version_minor;
558 unsigned long mode;
559 unsigned long aperture_base; /* physical address */
560 unsigned long aperture_size; /* bytes */
561 unsigned long memory_allowed; /* bytes */
562 unsigned long memory_used;
563
564 /* PCI information */
565 unsigned short id_vendor;
566 unsigned short id_device;
567};
568
569/**
570 * DRM_IOCTL_SG_ALLOC ioctl argument type.
571 */
572struct drm_scatter_gather {
573 unsigned long size; /**< In bytes -- will round to page boundary */
574 unsigned long handle; /**< Used for mapping / unmapping */
575};
576
577/**
578 * DRM_IOCTL_SET_VERSION ioctl argument type.
579 */
580struct drm_set_version {
581 int drm_di_major;
582 int drm_di_minor;
583 int drm_dd_major;
584 int drm_dd_minor;
585};
586
587/** DRM_IOCTL_GEM_CLOSE ioctl argument type */
588struct drm_gem_close {
589 /** Handle of the object to be closed. */
590 __u32 handle;
591 __u32 pad;
592};
593
594/** DRM_IOCTL_GEM_FLINK ioctl argument type */
595struct drm_gem_flink {
596 /** Handle for the object being named */
597 __u32 handle;
598
599 /** Returned global name */
600 __u32 name;
601};
602
603/** DRM_IOCTL_GEM_OPEN ioctl argument type */
604struct drm_gem_open {
605 /** Name of object being opened */
606 __u32 name;
607
608 /** Returned handle for the object */
609 __u32 handle;
610
611 /** Returned size of the object */
612 __u64 size;
613};
614
615/** DRM_IOCTL_GET_CAP ioctl argument type */
616struct drm_get_cap {
617 __u64 capability;
618 __u64 value;
619};
620
621/**
622 * DRM_CLIENT_CAP_STEREO_3D
623 *
624 * if set to 1, the DRM core will expose the stereo 3D capabilities of the
625 * monitor by advertising the supported 3D layouts in the flags of struct
626 * drm_mode_modeinfo.
627 */
628#define DRM_CLIENT_CAP_STEREO_3D 1
629
630/**
631 * DRM_CLIENT_CAP_UNIVERSAL_PLANES
632 *
633 * if set to 1, the DRM core will expose the full universal plane list
634 * (including primary and cursor planes).
635 */
636#define DRM_CLIENT_CAP_UNIVERSAL_PLANES 2
637
638/**
639 * DRM_CLIENT_CAP_ATOMIC
640 *
641 * If set to 1, the DRM core will allow atomic modesetting requests.
642 */
643#define DRM_CLIENT_CAP_ATOMIC 3
644
645/** DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */
646struct drm_set_client_cap {
647 __u64 capability;
648 __u64 value;
649};
650
651#define DRM_CLOEXEC O_CLOEXEC
652struct drm_prime_handle {
653 __u32 handle;
654
655 /** Flags.. only applicable for handle->fd */
656 __u32 flags;
657
658 /** Returned dmabuf file descriptor */
659 __s32 fd;
660};
661
662#include "drm_mode.h"
663
664#define DRM_IOCTL_BASE 'd'
665#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
666#define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type)
667#define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type)
668#define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type)
669
670#define DRM_IOCTL_VERSION DRM_IOWR(0x00, struct drm_version)
671#define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, struct drm_unique)
672#define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, struct drm_auth)
673#define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, struct drm_irq_busid)
674#define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, struct drm_map)
675#define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, struct drm_client)
676#define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats)
677#define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, struct drm_set_version)
678#define DRM_IOCTL_MODESET_CTL DRM_IOW(0x08, struct drm_modeset_ctl)
679#define DRM_IOCTL_GEM_CLOSE DRM_IOW (0x09, struct drm_gem_close)
680#define DRM_IOCTL_GEM_FLINK DRM_IOWR(0x0a, struct drm_gem_flink)
681#define DRM_IOCTL_GEM_OPEN DRM_IOWR(0x0b, struct drm_gem_open)
682#define DRM_IOCTL_GET_CAP DRM_IOWR(0x0c, struct drm_get_cap)
683#define DRM_IOCTL_SET_CLIENT_CAP DRM_IOW( 0x0d, struct drm_set_client_cap)
684
685#define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, struct drm_unique)
686#define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, struct drm_auth)
687#define DRM_IOCTL_BLOCK DRM_IOWR(0x12, struct drm_block)
688#define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, struct drm_block)
689#define DRM_IOCTL_CONTROL DRM_IOW( 0x14, struct drm_control)
690#define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, struct drm_map)
691#define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, struct drm_buf_desc)
692#define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, struct drm_buf_desc)
693#define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, struct drm_buf_info)
694#define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, struct drm_buf_map)
695#define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, struct drm_buf_free)
696
697#define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, struct drm_map)
698
699#define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, struct drm_ctx_priv_map)
700#define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, struct drm_ctx_priv_map)
701
702#define DRM_IOCTL_SET_MASTER DRM_IO(0x1e)
703#define DRM_IOCTL_DROP_MASTER DRM_IO(0x1f)
704
705#define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, struct drm_ctx)
706#define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, struct drm_ctx)
707#define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, struct drm_ctx)
708#define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, struct drm_ctx)
709#define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, struct drm_ctx)
710#define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, struct drm_ctx)
711#define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, struct drm_ctx_res)
712#define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, struct drm_draw)
713#define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, struct drm_draw)
714#define DRM_IOCTL_DMA DRM_IOWR(0x29, struct drm_dma)
715#define DRM_IOCTL_LOCK DRM_IOW( 0x2a, struct drm_lock)
716#define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, struct drm_lock)
717#define DRM_IOCTL_FINISH DRM_IOW( 0x2c, struct drm_lock)
718
719#define DRM_IOCTL_PRIME_HANDLE_TO_FD DRM_IOWR(0x2d, struct drm_prime_handle)
720#define DRM_IOCTL_PRIME_FD_TO_HANDLE DRM_IOWR(0x2e, struct drm_prime_handle)
721
722#define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30)
723#define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31)
724#define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, struct drm_agp_mode)
725#define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, struct drm_agp_info)
726#define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, struct drm_agp_buffer)
727#define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, struct drm_agp_buffer)
728#define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding)
729#define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding)
730
731#define DRM_IOCTL_SG_ALLOC DRM_IOWR(0x38, struct drm_scatter_gather)
732#define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather)
733
734#define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank)
735
736#define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw)
737
738#define DRM_IOCTL_MODE_GETRESOURCES DRM_IOWR(0xA0, struct drm_mode_card_res)
739#define DRM_IOCTL_MODE_GETCRTC DRM_IOWR(0xA1, struct drm_mode_crtc)
740#define DRM_IOCTL_MODE_SETCRTC DRM_IOWR(0xA2, struct drm_mode_crtc)
741#define DRM_IOCTL_MODE_CURSOR DRM_IOWR(0xA3, struct drm_mode_cursor)
742#define DRM_IOCTL_MODE_GETGAMMA DRM_IOWR(0xA4, struct drm_mode_crtc_lut)
743#define DRM_IOCTL_MODE_SETGAMMA DRM_IOWR(0xA5, struct drm_mode_crtc_lut)
744#define DRM_IOCTL_MODE_GETENCODER DRM_IOWR(0xA6, struct drm_mode_get_encoder)
745#define DRM_IOCTL_MODE_GETCONNECTOR DRM_IOWR(0xA7, struct drm_mode_get_connector)
746#define DRM_IOCTL_MODE_ATTACHMODE DRM_IOWR(0xA8, struct drm_mode_mode_cmd)
747#define DRM_IOCTL_MODE_DETACHMODE DRM_IOWR(0xA9, struct drm_mode_mode_cmd)
748
749#define DRM_IOCTL_MODE_GETPROPERTY DRM_IOWR(0xAA, struct drm_mode_get_property)
750#define DRM_IOCTL_MODE_SETPROPERTY DRM_IOWR(0xAB, struct drm_mode_connector_set_property)
751#define DRM_IOCTL_MODE_GETPROPBLOB DRM_IOWR(0xAC, struct drm_mode_get_blob)
752#define DRM_IOCTL_MODE_GETFB DRM_IOWR(0xAD, struct drm_mode_fb_cmd)
753#define DRM_IOCTL_MODE_ADDFB DRM_IOWR(0xAE, struct drm_mode_fb_cmd)
754#define DRM_IOCTL_MODE_RMFB DRM_IOWR(0xAF, unsigned int)
755#define DRM_IOCTL_MODE_PAGE_FLIP DRM_IOWR(0xB0, struct drm_mode_crtc_page_flip)
756#define DRM_IOCTL_MODE_DIRTYFB DRM_IOWR(0xB1, struct drm_mode_fb_dirty_cmd)
757
758#define DRM_IOCTL_MODE_CREATE_DUMB DRM_IOWR(0xB2, struct drm_mode_create_dumb)
759#define DRM_IOCTL_MODE_MAP_DUMB DRM_IOWR(0xB3, struct drm_mode_map_dumb)
760#define DRM_IOCTL_MODE_DESTROY_DUMB DRM_IOWR(0xB4, struct drm_mode_destroy_dumb)
761#define DRM_IOCTL_MODE_GETPLANERESOURCES DRM_IOWR(0xB5, struct drm_mode_get_plane_res)
762#define DRM_IOCTL_MODE_GETPLANE DRM_IOWR(0xB6, struct drm_mode_get_plane)
763#define DRM_IOCTL_MODE_SETPLANE DRM_IOWR(0xB7, struct drm_mode_set_plane)
764#define DRM_IOCTL_MODE_ADDFB2 DRM_IOWR(0xB8, struct drm_mode_fb_cmd2)
765#define DRM_IOCTL_MODE_OBJ_GETPROPERTIES DRM_IOWR(0xB9, struct drm_mode_obj_get_properties)
766#define DRM_IOCTL_MODE_OBJ_SETPROPERTY DRM_IOWR(0xBA, struct drm_mode_obj_set_property)
767#define DRM_IOCTL_MODE_CURSOR2 DRM_IOWR(0xBB, struct drm_mode_cursor2)
768#define DRM_IOCTL_MODE_ATOMIC DRM_IOWR(0xBC, struct drm_mode_atomic)
769#define DRM_IOCTL_MODE_CREATEPROPBLOB DRM_IOWR(0xBD, struct drm_mode_create_blob)
770#define DRM_IOCTL_MODE_DESTROYPROPBLOB DRM_IOWR(0xBE, struct drm_mode_destroy_blob)
771
772/**
773 * Device specific ioctls should only be in their respective headers
774 * The device specific ioctl range is from 0x40 to 0x99.
775 * Generic IOCTLS restart at 0xA0.
776 *
777 * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and
778 * drmCommandReadWrite().
779 */
780#define DRM_COMMAND_BASE 0x40
781#define DRM_COMMAND_END 0xA0
782
783/**
784 * Header for events written back to userspace on the drm fd. The
785 * type defines the type of event, the length specifies the total
786 * length of the event (including the header), and user_data is
787 * typically a 64 bit value passed with the ioctl that triggered the
788 * event. A read on the drm fd will always only return complete
789 * events, that is, if for example the read buffer is 100 bytes, and
790 * there are two 64 byte events pending, only one will be returned.
791 *
792 * Event types 0 - 0x7fffffff are generic drm events, 0x80000000 and
793 * up are chipset specific.
794 */
795struct drm_event {
796 __u32 type;
797 __u32 length;
798};
799
800#define DRM_EVENT_VBLANK 0x01
801#define DRM_EVENT_FLIP_COMPLETE 0x02
802
803struct drm_event_vblank {
804 struct drm_event base;
805 __u64 user_data;
806 __u32 tv_sec;
807 __u32 tv_usec;
808 __u32 sequence;
809 __u32 reserved;
810};
811
812#define DRM_CAP_DUMB_BUFFER 0x1
813#define DRM_CAP_VBLANK_HIGH_CRTC 0x2
814#define DRM_CAP_DUMB_PREFERRED_DEPTH 0x3
815#define DRM_CAP_DUMB_PREFER_SHADOW 0x4
816#define DRM_CAP_PRIME 0x5
817#define DRM_CAP_TIMESTAMP_MONOTONIC 0x6
818#define DRM_CAP_ASYNC_PAGE_FLIP 0x7
819#define DRM_CAP_ADDFB2_MODIFIERS 0x10
820
821#define DRM_PRIME_CAP_IMPORT 0x1
822#define DRM_PRIME_CAP_EXPORT 0x2
823
824/* typedef area */
825typedef struct drm_clip_rect drm_clip_rect_t;
826typedef struct drm_drawable_info drm_drawable_info_t;
827typedef struct drm_tex_region drm_tex_region_t;
828typedef struct drm_hw_lock drm_hw_lock_t;
829typedef struct drm_version drm_version_t;
830typedef struct drm_unique drm_unique_t;
831typedef struct drm_list drm_list_t;
832typedef struct drm_block drm_block_t;
833typedef struct drm_control drm_control_t;
834typedef enum drm_map_type drm_map_type_t;
835typedef enum drm_map_flags drm_map_flags_t;
836typedef struct drm_ctx_priv_map drm_ctx_priv_map_t;
837typedef struct drm_map drm_map_t;
838typedef struct drm_client drm_client_t;
839typedef enum drm_stat_type drm_stat_type_t;
840typedef struct drm_stats drm_stats_t;
841typedef enum drm_lock_flags drm_lock_flags_t;
842typedef struct drm_lock drm_lock_t;
843typedef enum drm_dma_flags drm_dma_flags_t;
844typedef struct drm_buf_desc drm_buf_desc_t;
845typedef struct drm_buf_info drm_buf_info_t;
846typedef struct drm_buf_free drm_buf_free_t;
847typedef struct drm_buf_pub drm_buf_pub_t;
848typedef struct drm_buf_map drm_buf_map_t;
849typedef struct drm_dma drm_dma_t;
850typedef union drm_wait_vblank drm_wait_vblank_t;
851typedef struct drm_agp_mode drm_agp_mode_t;
852typedef enum drm_ctx_flags drm_ctx_flags_t;
853typedef struct drm_ctx drm_ctx_t;
854typedef struct drm_ctx_res drm_ctx_res_t;
855typedef struct drm_draw drm_draw_t;
856typedef struct drm_update_draw drm_update_draw_t;
857typedef struct drm_auth drm_auth_t;
858typedef struct drm_irq_busid drm_irq_busid_t;
859typedef enum drm_vblank_seq_type drm_vblank_seq_type_t;
860
861typedef struct drm_agp_buffer drm_agp_buffer_t;
862typedef struct drm_agp_binding drm_agp_binding_t;
863typedef struct drm_agp_info drm_agp_info_t;
864typedef struct drm_scatter_gather drm_scatter_gather_t;
865typedef struct drm_set_version drm_set_version_t;
866
867#endif
diff --git a/src/static_libs/libdrm/drm_fourcc.h b/src/static_libs/libdrm/drm_fourcc.h
new file mode 100644
index 0000000000..e741b09a00
--- /dev/null
+++ b/src/static_libs/libdrm/drm_fourcc.h
@@ -0,0 +1,223 @@
1/*
2 * Copyright 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24#ifndef DRM_FOURCC_H
25#define DRM_FOURCC_H
26
27#include <inttypes.h>
28
29#define fourcc_code(a,b,c,d) ((uint32_t)(a) | ((uint32_t)(b) << 8) | \
30 ((uint32_t)(c) << 16) | ((uint32_t)(d) << 24))
31
32#define DRM_FORMAT_BIG_ENDIAN (1<<31) /* format is big endian instead of little endian */
33
34/* color index */
35#define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
36
37/* 8 bpp RGB */
38#define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */
39#define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */
40
41/* 16 bpp RGB */
42#define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */
43#define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */
44#define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */
45#define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */
46
47#define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */
48#define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */
49#define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */
50#define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */
51
52#define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */
53#define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */
54#define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */
55#define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */
56
57#define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */
58#define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */
59#define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */
60#define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */
61
62#define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */
63#define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */
64
65/* 24 bpp RGB */
66#define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */
67#define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */
68
69/* 32 bpp RGB */
70#define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */
71#define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */
72#define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */
73#define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */
74
75#define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */
76#define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */
77#define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */
78#define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */
79
80#define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */
81#define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */
82#define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */
83#define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */
84
85#define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */
86#define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */
87#define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */
88#define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */
89
90/* packed YCbCr */
91#define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */
92#define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */
93#define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */
94#define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
95
96#define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
97
98/*
99 * 2 plane YCbCr
100 * index 0 = Y plane, [7:0] Y
101 * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian
102 * or
103 * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian
104 */
105#define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */
106#define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */
107#define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */
108#define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */
109
110/*
111 * 3 plane YCbCr
112 * index 0: Y plane, [7:0] Y
113 * index 1: Cb plane, [7:0] Cb
114 * index 2: Cr plane, [7:0] Cr
115 * or
116 * index 1: Cr plane, [7:0] Cr
117 * index 2: Cb plane, [7:0] Cb
118 */
119#define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */
120#define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */
121#define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */
122#define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */
123#define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */
124#define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */
125#define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */
126#define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */
127#define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */
128#define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */
129
130
131/*
132 * Format Modifiers:
133 *
134 * Format modifiers describe, typically, a re-ordering or modification
135 * of the data in a plane of an FB. This can be used to express tiled/
136 * swizzled formats, or compression, or a combination of the two.
137 *
138 * The upper 8 bits of the format modifier are a vendor-id as assigned
139 * below. The lower 56 bits are assigned as vendor sees fit.
140 */
141
142/* Vendor Ids: */
143#define DRM_FORMAT_MOD_NONE 0
144#define DRM_FORMAT_MOD_VENDOR_INTEL 0x01
145#define DRM_FORMAT_MOD_VENDOR_AMD 0x02
146#define DRM_FORMAT_MOD_VENDOR_NV 0x03
147#define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04
148#define DRM_FORMAT_MOD_VENDOR_QCOM 0x05
149/* add more to the end as needed */
150
151#define fourcc_mod_code(vendor, val) \
152 ((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | (val & 0x00ffffffffffffffULL))
153
154/*
155 * Format Modifier tokens:
156 *
157 * When adding a new token please document the layout with a code comment,
158 * similar to the fourcc codes above. drm_fourcc.h is considered the
159 * authoritative source for all of these.
160 */
161
162/* Intel framebuffer modifiers */
163
164/*
165 * Intel X-tiling layout
166 *
167 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
168 * in row-major layout. Within the tile bytes are laid out row-major, with
169 * a platform-dependent stride. On top of that the memory can apply
170 * platform-depending swizzling of some higher address bits into bit6.
171 *
172 * This format is highly platforms specific and not useful for cross-driver
173 * sharing. It exists since on a given platform it does uniquely identify the
174 * layout in a simple way for i915-specific userspace.
175 */
176#define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1)
177
178/*
179 * Intel Y-tiling layout
180 *
181 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
182 * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)
183 * chunks column-major, with a platform-dependent height. On top of that the
184 * memory can apply platform-depending swizzling of some higher address bits
185 * into bit6.
186 *
187 * This format is highly platforms specific and not useful for cross-driver
188 * sharing. It exists since on a given platform it does uniquely identify the
189 * layout in a simple way for i915-specific userspace.
190 */
191#define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2)
192
193/*
194 * Intel Yf-tiling layout
195 *
196 * This is a tiled layout using 4Kb tiles in row-major layout.
197 * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
198 * are arranged in four groups (two wide, two high) with column-major layout.
199 * Each group therefore consits out of four 256 byte units, which are also laid
200 * out as 2x2 column-major.
201 * 256 byte units are made out of four 64 byte blocks of pixels, producing
202 * either a square block or a 2:1 unit.
203 * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width
204 * in pixel depends on the pixel depth.
205 */
206#define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3)
207
208/*
209 * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
210 *
211 * Macroblocks are laid in a Z-shape, and each pixel data is following the
212 * standard NV12 style.
213 * As for NV12, an image is the result of two frame buffers: one for Y,
214 * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer).
215 * Alignment requirements are (for each buffer):
216 * - multiple of 128 pixels for the width
217 * - multiple of 32 pixels for the height
218 *
219 * For more information: see http://linuxtv.org/downloads/v4l-dvb-apis/re32.html
220 */
221#define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)
222
223#endif /* DRM_FOURCC_H */
diff --git a/src/static_libs/libdrm/drm_mode.h b/src/static_libs/libdrm/drm_mode.h
new file mode 100644
index 0000000000..115f36e452
--- /dev/null
+++ b/src/static_libs/libdrm/drm_mode.h
@@ -0,0 +1,556 @@
1/*
2 * Copyright (c) 2007 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007 Jakob Bornecrantz <wallbraker@gmail.com>
4 * Copyright (c) 2008 Red Hat Inc.
5 * Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA
6 * Copyright (c) 2007-2008 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
21 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * IN THE SOFTWARE.
25 */
26
27#ifndef _DRM_MODE_H
28#define _DRM_MODE_H
29
30#define DRM_DISPLAY_INFO_LEN 32
31#define DRM_CONNECTOR_NAME_LEN 32
32#define DRM_DISPLAY_MODE_LEN 32
33#define DRM_PROP_NAME_LEN 32
34
35#define DRM_MODE_TYPE_BUILTIN (1<<0)
36#define DRM_MODE_TYPE_CLOCK_C ((1<<1) | DRM_MODE_TYPE_BUILTIN)
37#define DRM_MODE_TYPE_CRTC_C ((1<<2) | DRM_MODE_TYPE_BUILTIN)
38#define DRM_MODE_TYPE_PREFERRED (1<<3)
39#define DRM_MODE_TYPE_DEFAULT (1<<4)
40#define DRM_MODE_TYPE_USERDEF (1<<5)
41#define DRM_MODE_TYPE_DRIVER (1<<6)
42
43/* Video mode flags */
44/* bit compatible with the xorg definitions. */
45#define DRM_MODE_FLAG_PHSYNC (1<<0)
46#define DRM_MODE_FLAG_NHSYNC (1<<1)
47#define DRM_MODE_FLAG_PVSYNC (1<<2)
48#define DRM_MODE_FLAG_NVSYNC (1<<3)
49#define DRM_MODE_FLAG_INTERLACE (1<<4)
50#define DRM_MODE_FLAG_DBLSCAN (1<<5)
51#define DRM_MODE_FLAG_CSYNC (1<<6)
52#define DRM_MODE_FLAG_PCSYNC (1<<7)
53#define DRM_MODE_FLAG_NCSYNC (1<<8)
54#define DRM_MODE_FLAG_HSKEW (1<<9) /* hskew provided */
55#define DRM_MODE_FLAG_BCAST (1<<10)
56#define DRM_MODE_FLAG_PIXMUX (1<<11)
57#define DRM_MODE_FLAG_DBLCLK (1<<12)
58#define DRM_MODE_FLAG_CLKDIV2 (1<<13)
59#define DRM_MODE_FLAG_3D_MASK (0x1f<<14)
60#define DRM_MODE_FLAG_3D_NONE (0<<14)
61#define DRM_MODE_FLAG_3D_FRAME_PACKING (1<<14)
62#define DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE (2<<14)
63#define DRM_MODE_FLAG_3D_LINE_ALTERNATIVE (3<<14)
64#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL (4<<14)
65#define DRM_MODE_FLAG_3D_L_DEPTH (5<<14)
66#define DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH (6<<14)
67#define DRM_MODE_FLAG_3D_TOP_AND_BOTTOM (7<<14)
68#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF (8<<14)
69
70
71/* DPMS flags */
72/* bit compatible with the xorg definitions. */
73#define DRM_MODE_DPMS_ON 0
74#define DRM_MODE_DPMS_STANDBY 1
75#define DRM_MODE_DPMS_SUSPEND 2
76#define DRM_MODE_DPMS_OFF 3
77
78/* Scaling mode options */
79#define DRM_MODE_SCALE_NONE 0 /* Unmodified timing (display or
80 software can still scale) */
81#define DRM_MODE_SCALE_FULLSCREEN 1 /* Full screen, ignore aspect */
82#define DRM_MODE_SCALE_CENTER 2 /* Centered, no scaling */
83#define DRM_MODE_SCALE_ASPECT 3 /* Full screen, preserve aspect */
84
85/* Dithering mode options */
86#define DRM_MODE_DITHERING_OFF 0
87#define DRM_MODE_DITHERING_ON 1
88#define DRM_MODE_DITHERING_AUTO 2
89
90/* Dirty info options */
91#define DRM_MODE_DIRTY_OFF 0
92#define DRM_MODE_DIRTY_ON 1
93#define DRM_MODE_DIRTY_ANNOTATE 2
94
95struct drm_mode_modeinfo {
96 __u32 clock;
97 __u16 hdisplay, hsync_start, hsync_end, htotal, hskew;
98 __u16 vdisplay, vsync_start, vsync_end, vtotal, vscan;
99
100 __u32 vrefresh;
101
102 __u32 flags;
103 __u32 type;
104 char name[DRM_DISPLAY_MODE_LEN];
105};
106
107struct drm_mode_card_res {
108 __u64 fb_id_ptr;
109 __u64 crtc_id_ptr;
110 __u64 connector_id_ptr;
111 __u64 encoder_id_ptr;
112 __u32 count_fbs;
113 __u32 count_crtcs;
114 __u32 count_connectors;
115 __u32 count_encoders;
116 __u32 min_width, max_width;
117 __u32 min_height, max_height;
118};
119
120struct drm_mode_crtc {
121 __u64 set_connectors_ptr;
122 __u32 count_connectors;
123
124 __u32 crtc_id; /**< Id */
125 __u32 fb_id; /**< Id of framebuffer */
126
127 __u32 x, y; /**< Position on the frameuffer */
128
129 __u32 gamma_size;
130 __u32 mode_valid;
131 struct drm_mode_modeinfo mode;
132};
133
134#define DRM_MODE_PRESENT_TOP_FIELD (1<<0)
135#define DRM_MODE_PRESENT_BOTTOM_FIELD (1<<1)
136
137/* Planes blend with or override other bits on the CRTC */
138struct drm_mode_set_plane {
139 __u32 plane_id;
140 __u32 crtc_id;
141 __u32 fb_id; /* fb object contains surface format type */
142 __u32 flags;
143
144 /* Signed dest location allows it to be partially off screen */
145 __s32 crtc_x, crtc_y;
146 __u32 crtc_w, crtc_h;
147
148 /* Source values are 16.16 fixed point */
149 __u32 src_x, src_y;
150 __u32 src_h, src_w;
151};
152
153struct drm_mode_get_plane {
154 __u32 plane_id;
155
156 __u32 crtc_id;
157 __u32 fb_id;
158
159 __u32 possible_crtcs;
160 __u32 gamma_size;
161
162 __u32 count_format_types;
163 __u64 format_type_ptr;
164};
165
166struct drm_mode_get_plane_res {
167 __u64 plane_id_ptr;
168 __u32 count_planes;
169};
170
171#define DRM_MODE_ENCODER_NONE 0
172#define DRM_MODE_ENCODER_DAC 1
173#define DRM_MODE_ENCODER_TMDS 2
174#define DRM_MODE_ENCODER_LVDS 3
175#define DRM_MODE_ENCODER_TVDAC 4
176#define DRM_MODE_ENCODER_VIRTUAL 5
177#define DRM_MODE_ENCODER_DSI 6
178#define DRM_MODE_ENCODER_DPMST 7
179
180struct drm_mode_get_encoder {
181 __u32 encoder_id;
182 __u32 encoder_type;
183
184 __u32 crtc_id; /**< Id of crtc */
185
186 __u32 possible_crtcs;
187 __u32 possible_clones;
188};
189
190/* This is for connectors with multiple signal types. */
191/* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */
192#define DRM_MODE_SUBCONNECTOR_Automatic 0
193#define DRM_MODE_SUBCONNECTOR_Unknown 0
194#define DRM_MODE_SUBCONNECTOR_DVID 3
195#define DRM_MODE_SUBCONNECTOR_DVIA 4
196#define DRM_MODE_SUBCONNECTOR_Composite 5
197#define DRM_MODE_SUBCONNECTOR_SVIDEO 6
198#define DRM_MODE_SUBCONNECTOR_Component 8
199#define DRM_MODE_SUBCONNECTOR_SCART 9
200
201#define DRM_MODE_CONNECTOR_Unknown 0
202#define DRM_MODE_CONNECTOR_VGA 1
203#define DRM_MODE_CONNECTOR_DVII 2
204#define DRM_MODE_CONNECTOR_DVID 3
205#define DRM_MODE_CONNECTOR_DVIA 4
206#define DRM_MODE_CONNECTOR_Composite 5
207#define DRM_MODE_CONNECTOR_SVIDEO 6
208#define DRM_MODE_CONNECTOR_LVDS 7
209#define DRM_MODE_CONNECTOR_Component 8
210#define DRM_MODE_CONNECTOR_9PinDIN 9
211#define DRM_MODE_CONNECTOR_DisplayPort 10
212#define DRM_MODE_CONNECTOR_HDMIA 11
213#define DRM_MODE_CONNECTOR_HDMIB 12
214#define DRM_MODE_CONNECTOR_TV 13
215#define DRM_MODE_CONNECTOR_eDP 14
216#define DRM_MODE_CONNECTOR_VIRTUAL 15
217#define DRM_MODE_CONNECTOR_DSI 16
218
219struct drm_mode_get_connector {
220
221 __u64 encoders_ptr;
222 __u64 modes_ptr;
223 __u64 props_ptr;
224 __u64 prop_values_ptr;
225
226 __u32 count_modes;
227 __u32 count_props;
228 __u32 count_encoders;
229
230 __u32 encoder_id; /**< Current Encoder */
231 __u32 connector_id; /**< Id */
232 __u32 connector_type;
233 __u32 connector_type_id;
234
235 __u32 connection;
236 __u32 mm_width, mm_height; /**< HxW in millimeters */
237 __u32 subpixel;
238};
239
240#define DRM_MODE_PROP_PENDING (1<<0)
241#define DRM_MODE_PROP_RANGE (1<<1)
242#define DRM_MODE_PROP_IMMUTABLE (1<<2)
243#define DRM_MODE_PROP_ENUM (1<<3) /* enumerated type with text strings */
244#define DRM_MODE_PROP_BLOB (1<<4)
245#define DRM_MODE_PROP_BITMASK (1<<5) /* bitmask of enumerated types */
246
247/* non-extended types: legacy bitmask, one bit per type: */
248#define DRM_MODE_PROP_LEGACY_TYPE ( \
249 DRM_MODE_PROP_RANGE | \
250 DRM_MODE_PROP_ENUM | \
251 DRM_MODE_PROP_BLOB | \
252 DRM_MODE_PROP_BITMASK)
253
254/* extended-types: rather than continue to consume a bit per type,
255 * grab a chunk of the bits to use as integer type id.
256 */
257#define DRM_MODE_PROP_EXTENDED_TYPE 0x0000ffc0
258#define DRM_MODE_PROP_TYPE(n) ((n) << 6)
259#define DRM_MODE_PROP_OBJECT DRM_MODE_PROP_TYPE(1)
260#define DRM_MODE_PROP_SIGNED_RANGE DRM_MODE_PROP_TYPE(2)
261
262struct drm_mode_property_enum {
263 __u64 value;
264 char name[DRM_PROP_NAME_LEN];
265};
266
267struct drm_mode_get_property {
268 __u64 values_ptr; /* values and blob lengths */
269 __u64 enum_blob_ptr; /* enum and blob id ptrs */
270
271 __u32 prop_id;
272 __u32 flags;
273 char name[DRM_PROP_NAME_LEN];
274
275 __u32 count_values;
276 __u32 count_enum_blobs;
277};
278
279struct drm_mode_connector_set_property {
280 __u64 value;
281 __u32 prop_id;
282 __u32 connector_id;
283};
284
285#define DRM_MODE_OBJECT_CRTC 0xcccccccc
286#define DRM_MODE_OBJECT_CONNECTOR 0xc0c0c0c0
287#define DRM_MODE_OBJECT_ENCODER 0xe0e0e0e0
288#define DRM_MODE_OBJECT_MODE 0xdededede
289#define DRM_MODE_OBJECT_PROPERTY 0xb0b0b0b0
290#define DRM_MODE_OBJECT_FB 0xfbfbfbfb
291#define DRM_MODE_OBJECT_BLOB 0xbbbbbbbb
292#define DRM_MODE_OBJECT_PLANE 0xeeeeeeee
293
294struct drm_mode_obj_get_properties {
295 __u64 props_ptr;
296 __u64 prop_values_ptr;
297 __u32 count_props;
298 __u32 obj_id;
299 __u32 obj_type;
300};
301
302struct drm_mode_obj_set_property {
303 __u64 value;
304 __u32 prop_id;
305 __u32 obj_id;
306 __u32 obj_type;
307};
308
309struct drm_mode_get_blob {
310 __u32 blob_id;
311 __u32 length;
312 __u64 data;
313};
314
315struct drm_mode_fb_cmd {
316 __u32 fb_id;
317 __u32 width, height;
318 __u32 pitch;
319 __u32 bpp;
320 __u32 depth;
321 /* driver specific handle */
322 __u32 handle;
323};
324
325#define DRM_MODE_FB_INTERLACED (1<<0) /* for interlaced framebuffers */
326#define DRM_MODE_FB_MODIFIERS (1<<1) /* enables ->modifer[] */
327
328struct drm_mode_fb_cmd2 {
329 __u32 fb_id;
330 __u32 width, height;
331 __u32 pixel_format; /* fourcc code from drm_fourcc.h */
332 __u32 flags;
333
334 /*
335 * In case of planar formats, this ioctl allows up to 4
336 * buffer objects with offsets and pitches per plane.
337 * The pitch and offset order is dictated by the fourcc,
338 * e.g. NV12 (http://fourcc.org/yuv.php#NV12) is described as:
339 *
340 * YUV 4:2:0 image with a plane of 8 bit Y samples
341 * followed by an interleaved U/V plane containing
342 * 8 bit 2x2 subsampled colour difference samples.
343 *
344 * So it would consist of Y as offset[0] and UV as
345 * offset[1]. Note that offset[0] will generally
346 * be 0.
347 *
348 * To accommodate tiled, compressed, etc formats, a per-plane
349 * modifier can be specified. The default value of zero
350 * indicates "native" format as specified by the fourcc.
351 * Vendor specific modifier token. This allows, for example,
352 * different tiling/swizzling pattern on different planes.
353 * See discussion above of DRM_FORMAT_MOD_xxx.
354 */
355 __u32 handles[4];
356 __u32 pitches[4]; /* pitch for each plane */
357 __u32 offsets[4]; /* offset of each plane */
358 __u64 modifier[4]; /* ie, tiling, compressed (per plane) */
359};
360
361#define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01
362#define DRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02
363#define DRM_MODE_FB_DIRTY_FLAGS 0x03
364
365/*
366 * Mark a region of a framebuffer as dirty.
367 *
368 * Some hardware does not automatically update display contents
369 * as a hardware or software draw to a framebuffer. This ioctl
370 * allows userspace to tell the kernel and the hardware what
371 * regions of the framebuffer have changed.
372 *
373 * The kernel or hardware is free to update more then just the
374 * region specified by the clip rects. The kernel or hardware
375 * may also delay and/or coalesce several calls to dirty into a
376 * single update.
377 *
378 * Userspace may annotate the updates, the annotates are a
379 * promise made by the caller that the change is either a copy
380 * of pixels or a fill of a single color in the region specified.
381 *
382 * If the DRM_MODE_FB_DIRTY_ANNOTATE_COPY flag is given then
383 * the number of updated regions are half of num_clips given,
384 * where the clip rects are paired in src and dst. The width and
385 * height of each one of the pairs must match.
386 *
387 * If the DRM_MODE_FB_DIRTY_ANNOTATE_FILL flag is given the caller
388 * promises that the region specified of the clip rects is filled
389 * completely with a single color as given in the color argument.
390 */
391
392struct drm_mode_fb_dirty_cmd {
393 __u32 fb_id;
394 __u32 flags;
395 __u32 color;
396 __u32 num_clips;
397 __u64 clips_ptr;
398};
399
400struct drm_mode_mode_cmd {
401 __u32 connector_id;
402 struct drm_mode_modeinfo mode;
403};
404
405#define DRM_MODE_CURSOR_BO (1<<0)
406#define DRM_MODE_CURSOR_MOVE (1<<1)
407
408/*
409 * depending on the value in flags diffrent members are used.
410 *
411 * CURSOR_BO uses
412 * crtc
413 * width
414 * height
415 * handle - if 0 turns the cursor of
416 *
417 * CURSOR_MOVE uses
418 * crtc
419 * x
420 * y
421 */
422struct drm_mode_cursor {
423 __u32 flags;
424 __u32 crtc_id;
425 __s32 x;
426 __s32 y;
427 __u32 width;
428 __u32 height;
429 /* driver specific handle */
430 __u32 handle;
431};
432
433struct drm_mode_cursor2 {
434 __u32 flags;
435 __u32 crtc_id;
436 __s32 x;
437 __s32 y;
438 __u32 width;
439 __u32 height;
440 /* driver specific handle */
441 __u32 handle;
442 __s32 hot_x;
443 __s32 hot_y;
444};
445
446struct drm_mode_crtc_lut {
447 __u32 crtc_id;
448 __u32 gamma_size;
449
450 /* pointers to arrays */
451 __u64 red;
452 __u64 green;
453 __u64 blue;
454};
455
456#define DRM_MODE_PAGE_FLIP_EVENT 0x01
457#define DRM_MODE_PAGE_FLIP_ASYNC 0x02
458#define DRM_MODE_PAGE_FLIP_FLAGS (DRM_MODE_PAGE_FLIP_EVENT|DRM_MODE_PAGE_FLIP_ASYNC)
459
460/*
461 * Request a page flip on the specified crtc.
462 *
463 * This ioctl will ask KMS to schedule a page flip for the specified
464 * crtc. Once any pending rendering targeting the specified fb (as of
465 * ioctl time) has completed, the crtc will be reprogrammed to display
466 * that fb after the next vertical refresh. The ioctl returns
467 * immediately, but subsequent rendering to the current fb will block
468 * in the execbuffer ioctl until the page flip happens. If a page
469 * flip is already pending as the ioctl is called, EBUSY will be
470 * returned.
471 *
472 * The ioctl supports one flag, DRM_MODE_PAGE_FLIP_EVENT, which will
473 * request that drm sends back a vblank event (see drm.h: struct
474 * drm_event_vblank) when the page flip is done. The user_data field
475 * passed in with this ioctl will be returned as the user_data field
476 * in the vblank event struct.
477 *
478 * The reserved field must be zero until we figure out something
479 * clever to use it for.
480 */
481
482struct drm_mode_crtc_page_flip {
483 __u32 crtc_id;
484 __u32 fb_id;
485 __u32 flags;
486 __u32 reserved;
487 __u64 user_data;
488};
489
490/* create a dumb scanout buffer */
491struct drm_mode_create_dumb {
492 __u32 height;
493 __u32 width;
494 __u32 bpp;
495 __u32 flags;
496 /* handle, pitch, size will be returned */
497 __u32 handle;
498 __u32 pitch;
499 __u64 size;
500};
501
502/* set up for mmap of a dumb scanout buffer */
503struct drm_mode_map_dumb {
504 /** Handle for the object being mapped. */
505 __u32 handle;
506 __u32 pad;
507 /**
508 * Fake offset to use for subsequent mmap call
509 *
510 * This is a fixed-size type for 32/64 compatibility.
511 */
512 __u64 offset;
513};
514
515struct drm_mode_destroy_dumb {
516 __u32 handle;
517};
518
519/* page-flip flags are valid, plus: */
520#define DRM_MODE_ATOMIC_TEST_ONLY 0x0100
521#define DRM_MODE_ATOMIC_NONBLOCK 0x0200
522#define DRM_MODE_ATOMIC_ALLOW_MODESET 0x0400
523
524struct drm_mode_atomic {
525 __u32 flags;
526 __u32 count_objs;
527 __u64 objs_ptr;
528 __u64 count_props_ptr;
529 __u64 props_ptr;
530 __u64 prop_values_ptr;
531 __u64 reserved;
532 __u64 user_data;
533};
534
535/**
536 * Create a new 'blob' data property, copying length bytes from data pointer,
537 * and returning new blob ID.
538 */
539struct drm_mode_create_blob {
540 /** Pointer to data to copy. */
541 __u64 data;
542 /** Length of data to copy. */
543 __u32 length;
544 /** Return: new property ID. */
545 __u32 blob_id;
546};
547
548/**
549 * Destroy a user-created blob property.
550 */
551struct drm_mode_destroy_blob {
552 __u32 blob_id;
553};
554
555
556#endif
diff --git a/src/static_libs/libdrm/i915_drm.h b/src/static_libs/libdrm/i915_drm.h
new file mode 100644
index 0000000000..0e51d4214e
--- /dev/null
+++ b/src/static_libs/libdrm/i915_drm.h
@@ -0,0 +1,1146 @@
1/*
2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
15 * of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26
27#ifndef _I915_DRM_H_
28#define _I915_DRM_H_
29
30#include "drm.h"
31
32/* Please note that modifications to all structs defined here are
33 * subject to backwards-compatibility constraints.
34 */
35
36/**
37 * DOC: uevents generated by i915 on it's device node
38 *
39 * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch
40 * event from the gpu l3 cache. Additional information supplied is ROW,
41 * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep
42 * track of these events and if a specific cache-line seems to have a
43 * persistent error remap it with the l3 remapping tool supplied in
44 * intel-gpu-tools. The value supplied with the event is always 1.
45 *
46 * I915_ERROR_UEVENT - Generated upon error detection, currently only via
47 * hangcheck. The error detection event is a good indicator of when things
48 * began to go badly. The value supplied with the event is a 1 upon error
49 * detection, and a 0 upon reset completion, signifying no more error
50 * exists. NOTE: Disabling hangcheck or reset via module parameter will
51 * cause the related events to not be seen.
52 *
53 * I915_RESET_UEVENT - Event is generated just before an attempt to reset the
54 * the GPU. The value supplied with the event is always 1. NOTE: Disable
55 * reset via module parameter will cause this event to not be seen.
56 */
57#define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR"
58#define I915_ERROR_UEVENT "ERROR"
59#define I915_RESET_UEVENT "RESET"
60
61/* Each region is a minimum of 16k, and there are at most 255 of them.
62 */
63#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
64 * of chars for next/prev indices */
65#define I915_LOG_MIN_TEX_REGION_SIZE 14
66
67typedef struct _drm_i915_init {
68 enum {
69 I915_INIT_DMA = 0x01,
70 I915_CLEANUP_DMA = 0x02,
71 I915_RESUME_DMA = 0x03
72 } func;
73 unsigned int mmio_offset;
74 int sarea_priv_offset;
75 unsigned int ring_start;
76 unsigned int ring_end;
77 unsigned int ring_size;
78 unsigned int front_offset;
79 unsigned int back_offset;
80 unsigned int depth_offset;
81 unsigned int w;
82 unsigned int h;
83 unsigned int pitch;
84 unsigned int pitch_bits;
85 unsigned int back_pitch;
86 unsigned int depth_pitch;
87 unsigned int cpp;
88 unsigned int chipset;
89} drm_i915_init_t;
90
91typedef struct _drm_i915_sarea {
92 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
93 int last_upload; /* last time texture was uploaded */
94 int last_enqueue; /* last time a buffer was enqueued */
95 int last_dispatch; /* age of the most recently dispatched buffer */
96 int ctxOwner; /* last context to upload state */
97 int texAge;
98 int pf_enabled; /* is pageflipping allowed? */
99 int pf_active;
100 int pf_current_page; /* which buffer is being displayed? */
101 int perf_boxes; /* performance boxes to be displayed */
102 int width, height; /* screen size in pixels */
103
104 drm_handle_t front_handle;
105 int front_offset;
106 int front_size;
107
108 drm_handle_t back_handle;
109 int back_offset;
110 int back_size;
111
112 drm_handle_t depth_handle;
113 int depth_offset;
114 int depth_size;
115
116 drm_handle_t tex_handle;
117 int tex_offset;
118 int tex_size;
119 int log_tex_granularity;
120 int pitch;
121 int rotation; /* 0, 90, 180 or 270 */
122 int rotated_offset;
123 int rotated_size;
124 int rotated_pitch;
125 int virtualX, virtualY;
126
127 unsigned int front_tiled;
128 unsigned int back_tiled;
129 unsigned int depth_tiled;
130 unsigned int rotated_tiled;
131 unsigned int rotated2_tiled;
132
133 int pipeA_x;
134 int pipeA_y;
135 int pipeA_w;
136 int pipeA_h;
137 int pipeB_x;
138 int pipeB_y;
139 int pipeB_w;
140 int pipeB_h;
141
142 /* fill out some space for old userspace triple buffer */
143 drm_handle_t unused_handle;
144 __u32 unused1, unused2, unused3;
145
146 /* buffer object handles for static buffers. May change
147 * over the lifetime of the client.
148 */
149 __u32 front_bo_handle;
150 __u32 back_bo_handle;
151 __u32 unused_bo_handle;
152 __u32 depth_bo_handle;
153
154} drm_i915_sarea_t;
155
156/* due to userspace building against these headers we need some compat here */
157#define planeA_x pipeA_x
158#define planeA_y pipeA_y
159#define planeA_w pipeA_w
160#define planeA_h pipeA_h
161#define planeB_x pipeB_x
162#define planeB_y pipeB_y
163#define planeB_w pipeB_w
164#define planeB_h pipeB_h
165
166/* Flags for perf_boxes
167 */
168#define I915_BOX_RING_EMPTY 0x1
169#define I915_BOX_FLIP 0x2
170#define I915_BOX_WAIT 0x4
171#define I915_BOX_TEXTURE_LOAD 0x8
172#define I915_BOX_LOST_CONTEXT 0x10
173
174/*
175 * i915 specific ioctls.
176 *
177 * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie
178 * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset
179 * against DRM_COMMAND_BASE and should be between [0x0, 0x60).
180 */
181#define DRM_I915_INIT 0x00
182#define DRM_I915_FLUSH 0x01
183#define DRM_I915_FLIP 0x02
184#define DRM_I915_BATCHBUFFER 0x03
185#define DRM_I915_IRQ_EMIT 0x04
186#define DRM_I915_IRQ_WAIT 0x05
187#define DRM_I915_GETPARAM 0x06
188#define DRM_I915_SETPARAM 0x07
189#define DRM_I915_ALLOC 0x08
190#define DRM_I915_FREE 0x09
191#define DRM_I915_INIT_HEAP 0x0a
192#define DRM_I915_CMDBUFFER 0x0b
193#define DRM_I915_DESTROY_HEAP 0x0c
194#define DRM_I915_SET_VBLANK_PIPE 0x0d
195#define DRM_I915_GET_VBLANK_PIPE 0x0e
196#define DRM_I915_VBLANK_SWAP 0x0f
197#define DRM_I915_HWS_ADDR 0x11
198#define DRM_I915_GEM_INIT 0x13
199#define DRM_I915_GEM_EXECBUFFER 0x14
200#define DRM_I915_GEM_PIN 0x15
201#define DRM_I915_GEM_UNPIN 0x16
202#define DRM_I915_GEM_BUSY 0x17
203#define DRM_I915_GEM_THROTTLE 0x18
204#define DRM_I915_GEM_ENTERVT 0x19
205#define DRM_I915_GEM_LEAVEVT 0x1a
206#define DRM_I915_GEM_CREATE 0x1b
207#define DRM_I915_GEM_PREAD 0x1c
208#define DRM_I915_GEM_PWRITE 0x1d
209#define DRM_I915_GEM_MMAP 0x1e
210#define DRM_I915_GEM_SET_DOMAIN 0x1f
211#define DRM_I915_GEM_SW_FINISH 0x20
212#define DRM_I915_GEM_SET_TILING 0x21
213#define DRM_I915_GEM_GET_TILING 0x22
214#define DRM_I915_GEM_GET_APERTURE 0x23
215#define DRM_I915_GEM_MMAP_GTT 0x24
216#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25
217#define DRM_I915_GEM_MADVISE 0x26
218#define DRM_I915_OVERLAY_PUT_IMAGE 0x27
219#define DRM_I915_OVERLAY_ATTRS 0x28
220#define DRM_I915_GEM_EXECBUFFER2 0x29
221#define DRM_I915_GET_SPRITE_COLORKEY 0x2a
222#define DRM_I915_SET_SPRITE_COLORKEY 0x2b
223#define DRM_I915_GEM_WAIT 0x2c
224#define DRM_I915_GEM_CONTEXT_CREATE 0x2d
225#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e
226#define DRM_I915_GEM_SET_CACHING 0x2f
227#define DRM_I915_GEM_GET_CACHING 0x30
228#define DRM_I915_REG_READ 0x31
229#define DRM_I915_GET_RESET_STATS 0x32
230#define DRM_I915_GEM_USERPTR 0x33
231#define DRM_I915_GEM_CONTEXT_GETPARAM 0x34
232#define DRM_I915_GEM_CONTEXT_SETPARAM 0x35
233
234#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
235#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
236#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
237#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
238#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
239#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
240#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
241#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
242#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
243#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
244#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
245#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
246#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
247#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
248#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
249#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
250#define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init)
251#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
252#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
253#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
254#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
255#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
256#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
257#define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching)
258#define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching)
259#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
260#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
261#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
262#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
263#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
264#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
265#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
266#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
267#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
268#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
269#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
270#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
271#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
272#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
273#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
274#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)
275#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
276#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
277#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
278#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
279#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
280#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
281#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
282#define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
283#define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr)
284#define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param)
285#define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param)
286
287/* Allow drivers to submit batchbuffers directly to hardware, relying
288 * on the security mechanisms provided by hardware.
289 */
290typedef struct drm_i915_batchbuffer {
291 int start; /* agp offset */
292 int used; /* nr bytes in use */
293 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
294 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
295 int num_cliprects; /* mulitpass with multiple cliprects? */
296 struct drm_clip_rect *cliprects; /* pointer to userspace cliprects */
297} drm_i915_batchbuffer_t;
298
299/* As above, but pass a pointer to userspace buffer which can be
300 * validated by the kernel prior to sending to hardware.
301 */
302typedef struct _drm_i915_cmdbuffer {
303 char *buf; /* pointer to userspace command buffer */
304 int sz; /* nr bytes in buf */
305 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
306 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
307 int num_cliprects; /* mulitpass with multiple cliprects? */
308 struct drm_clip_rect *cliprects; /* pointer to userspace cliprects */
309} drm_i915_cmdbuffer_t;
310
311/* Userspace can request & wait on irq's:
312 */
313typedef struct drm_i915_irq_emit {
314 int *irq_seq;
315} drm_i915_irq_emit_t;
316
317typedef struct drm_i915_irq_wait {
318 int irq_seq;
319} drm_i915_irq_wait_t;
320
321/* Ioctl to query kernel params:
322 */
323#define I915_PARAM_IRQ_ACTIVE 1
324#define I915_PARAM_ALLOW_BATCHBUFFER 2
325#define I915_PARAM_LAST_DISPATCH 3
326#define I915_PARAM_CHIPSET_ID 4
327#define I915_PARAM_HAS_GEM 5
328#define I915_PARAM_NUM_FENCES_AVAIL 6
329#define I915_PARAM_HAS_OVERLAY 7
330#define I915_PARAM_HAS_PAGEFLIPPING 8
331#define I915_PARAM_HAS_EXECBUF2 9
332#define I915_PARAM_HAS_BSD 10
333#define I915_PARAM_HAS_BLT 11
334#define I915_PARAM_HAS_RELAXED_FENCING 12
335#define I915_PARAM_HAS_COHERENT_RINGS 13
336#define I915_PARAM_HAS_EXEC_CONSTANTS 14
337#define I915_PARAM_HAS_RELAXED_DELTA 15
338#define I915_PARAM_HAS_GEN7_SOL_RESET 16
339#define I915_PARAM_HAS_LLC 17
340#define I915_PARAM_HAS_ALIASING_PPGTT 18
341#define I915_PARAM_HAS_WAIT_TIMEOUT 19
342#define I915_PARAM_HAS_SEMAPHORES 20
343#define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21
344#define I915_PARAM_HAS_VEBOX 22
345#define I915_PARAM_HAS_SECURE_BATCHES 23
346#define I915_PARAM_HAS_PINNED_BATCHES 24
347#define I915_PARAM_HAS_EXEC_NO_RELOC 25
348#define I915_PARAM_HAS_EXEC_HANDLE_LUT 26
349#define I915_PARAM_HAS_WT 27
350#define I915_PARAM_CMD_PARSER_VERSION 28
351#define I915_PARAM_HAS_COHERENT_PHYS_GTT 29
352#define I915_PARAM_MMAP_VERSION 30
353#define I915_PARAM_HAS_BSD2 31
354#define I915_PARAM_REVISION 32
355#define I915_PARAM_SUBSLICE_TOTAL 33
356#define I915_PARAM_EU_TOTAL 34
357#define I915_PARAM_HAS_GPU_RESET 35
358#define I915_PARAM_HAS_RESOURCE_STREAMER 36
359#define I915_PARAM_HAS_EXEC_SOFTPIN 37
360
361typedef struct drm_i915_getparam {
362 __s32 param;
363 /*
364 * WARNING: Using pointers instead of fixed-size u64 means we need to write
365 * compat32 code. Don't repeat this mistake.
366 */
367 int *value;
368} drm_i915_getparam_t;
369
370/* Ioctl to set kernel params:
371 */
372#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
373#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
374#define I915_SETPARAM_ALLOW_BATCHBUFFER 3
375#define I915_SETPARAM_NUM_USED_FENCES 4
376
377typedef struct drm_i915_setparam {
378 int param;
379 int value;
380} drm_i915_setparam_t;
381
382/* A memory manager for regions of shared memory:
383 */
384#define I915_MEM_REGION_AGP 1
385
386typedef struct drm_i915_mem_alloc {
387 int region;
388 int alignment;
389 int size;
390 int *region_offset; /* offset from start of fb or agp */
391} drm_i915_mem_alloc_t;
392
393typedef struct drm_i915_mem_free {
394 int region;
395 int region_offset;
396} drm_i915_mem_free_t;
397
398typedef struct drm_i915_mem_init_heap {
399 int region;
400 int size;
401 int start;
402} drm_i915_mem_init_heap_t;
403
404/* Allow memory manager to be torn down and re-initialized (eg on
405 * rotate):
406 */
407typedef struct drm_i915_mem_destroy_heap {
408 int region;
409} drm_i915_mem_destroy_heap_t;
410
411/* Allow X server to configure which pipes to monitor for vblank signals
412 */
413#define DRM_I915_VBLANK_PIPE_A 1
414#define DRM_I915_VBLANK_PIPE_B 2
415
416typedef struct drm_i915_vblank_pipe {
417 int pipe;
418} drm_i915_vblank_pipe_t;
419
420/* Schedule buffer swap at given vertical blank:
421 */
422typedef struct drm_i915_vblank_swap {
423 drm_drawable_t drawable;
424 enum drm_vblank_seq_type seqtype;
425 unsigned int sequence;
426} drm_i915_vblank_swap_t;
427
428typedef struct drm_i915_hws_addr {
429 __u64 addr;
430} drm_i915_hws_addr_t;
431
432struct drm_i915_gem_init {
433 /**
434 * Beginning offset in the GTT to be managed by the DRM memory
435 * manager.
436 */
437 __u64 gtt_start;
438 /**
439 * Ending offset in the GTT to be managed by the DRM memory
440 * manager.
441 */
442 __u64 gtt_end;
443};
444
445struct drm_i915_gem_create {
446 /**
447 * Requested size for the object.
448 *
449 * The (page-aligned) allocated size for the object will be returned.
450 */
451 __u64 size;
452 /**
453 * Returned handle for the object.
454 *
455 * Object handles are nonzero.
456 */
457 __u32 handle;
458 __u32 pad;
459};
460
461struct drm_i915_gem_pread {
462 /** Handle for the object being read. */
463 __u32 handle;
464 __u32 pad;
465 /** Offset into the object to read from */
466 __u64 offset;
467 /** Length of data to read */
468 __u64 size;
469 /**
470 * Pointer to write the data into.
471 *
472 * This is a fixed-size type for 32/64 compatibility.
473 */
474 __u64 data_ptr;
475};
476
477struct drm_i915_gem_pwrite {
478 /** Handle for the object being written to. */
479 __u32 handle;
480 __u32 pad;
481 /** Offset into the object to write to */
482 __u64 offset;
483 /** Length of data to write */
484 __u64 size;
485 /**
486 * Pointer to read the data from.
487 *
488 * This is a fixed-size type for 32/64 compatibility.
489 */
490 __u64 data_ptr;
491};
492
493struct drm_i915_gem_mmap {
494 /** Handle for the object being mapped. */
495 __u32 handle;
496 __u32 pad;
497 /** Offset in the object to map. */
498 __u64 offset;
499 /**
500 * Length of data to map.
501 *
502 * The value will be page-aligned.
503 */
504 __u64 size;
505 /**
506 * Returned pointer the data was mapped at.
507 *
508 * This is a fixed-size type for 32/64 compatibility.
509 */
510 __u64 addr_ptr;
511
512 /**
513 * Flags for extended behaviour.
514 *
515 * Added in version 2.
516 */
517 __u64 flags;
518#define I915_MMAP_WC 0x1
519};
520
521struct drm_i915_gem_mmap_gtt {
522 /** Handle for the object being mapped. */
523 __u32 handle;
524 __u32 pad;
525 /**
526 * Fake offset to use for subsequent mmap call
527 *
528 * This is a fixed-size type for 32/64 compatibility.
529 */
530 __u64 offset;
531};
532
533struct drm_i915_gem_set_domain {
534 /** Handle for the object */
535 __u32 handle;
536
537 /** New read domains */
538 __u32 read_domains;
539
540 /** New write domain */
541 __u32 write_domain;
542};
543
544struct drm_i915_gem_sw_finish {
545 /** Handle for the object */
546 __u32 handle;
547};
548
549struct drm_i915_gem_relocation_entry {
550 /**
551 * Handle of the buffer being pointed to by this relocation entry.
552 *
553 * It's appealing to make this be an index into the mm_validate_entry
554 * list to refer to the buffer, but this allows the driver to create
555 * a relocation list for state buffers and not re-write it per
556 * exec using the buffer.
557 */
558 __u32 target_handle;
559
560 /**
561 * Value to be added to the offset of the target buffer to make up
562 * the relocation entry.
563 */
564 __u32 delta;
565
566 /** Offset in the buffer the relocation entry will be written into */
567 __u64 offset;
568
569 /**
570 * Offset value of the target buffer that the relocation entry was last
571 * written as.
572 *
573 * If the buffer has the same offset as last time, we can skip syncing
574 * and writing the relocation. This value is written back out by
575 * the execbuffer ioctl when the relocation is written.
576 */
577 __u64 presumed_offset;
578
579 /**
580 * Target memory domains read by this operation.
581 */
582 __u32 read_domains;
583
584 /**
585 * Target memory domains written by this operation.
586 *
587 * Note that only one domain may be written by the whole
588 * execbuffer operation, so that where there are conflicts,
589 * the application will get -EINVAL back.
590 */
591 __u32 write_domain;
592};
593
594/** @{
595 * Intel memory domains
596 *
597 * Most of these just align with the various caches in
598 * the system and are used to flush and invalidate as
599 * objects end up cached in different domains.
600 */
601/** CPU cache */
602#define I915_GEM_DOMAIN_CPU 0x00000001
603/** Render cache, used by 2D and 3D drawing */
604#define I915_GEM_DOMAIN_RENDER 0x00000002
605/** Sampler cache, used by texture engine */
606#define I915_GEM_DOMAIN_SAMPLER 0x00000004
607/** Command queue, used to load batch buffers */
608#define I915_GEM_DOMAIN_COMMAND 0x00000008
609/** Instruction cache, used by shader programs */
610#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
611/** Vertex address cache */
612#define I915_GEM_DOMAIN_VERTEX 0x00000020
613/** GTT domain - aperture and scanout */
614#define I915_GEM_DOMAIN_GTT 0x00000040
615/** @} */
616
617struct drm_i915_gem_exec_object {
618 /**
619 * User's handle for a buffer to be bound into the GTT for this
620 * operation.
621 */
622 __u32 handle;
623
624 /** Number of relocations to be performed on this buffer */
625 __u32 relocation_count;
626 /**
627 * Pointer to array of struct drm_i915_gem_relocation_entry containing
628 * the relocations to be performed in this buffer.
629 */
630 __u64 relocs_ptr;
631
632 /** Required alignment in graphics aperture */
633 __u64 alignment;
634
635 /**
636 * Returned value of the updated offset of the object, for future
637 * presumed_offset writes.
638 */
639 __u64 offset;
640};
641
642struct drm_i915_gem_execbuffer {
643 /**
644 * List of buffers to be validated with their relocations to be
645 * performend on them.
646 *
647 * This is a pointer to an array of struct drm_i915_gem_validate_entry.
648 *
649 * These buffers must be listed in an order such that all relocations
650 * a buffer is performing refer to buffers that have already appeared
651 * in the validate list.
652 */
653 __u64 buffers_ptr;
654 __u32 buffer_count;
655
656 /** Offset in the batchbuffer to start execution from. */
657 __u32 batch_start_offset;
658 /** Bytes used in batchbuffer from batch_start_offset */
659 __u32 batch_len;
660 __u32 DR1;
661 __u32 DR4;
662 __u32 num_cliprects;
663 /** This is a struct drm_clip_rect *cliprects */
664 __u64 cliprects_ptr;
665};
666
667struct drm_i915_gem_exec_object2 {
668 /**
669 * User's handle for a buffer to be bound into the GTT for this
670 * operation.
671 */
672 __u32 handle;
673
674 /** Number of relocations to be performed on this buffer */
675 __u32 relocation_count;
676 /**
677 * Pointer to array of struct drm_i915_gem_relocation_entry containing
678 * the relocations to be performed in this buffer.
679 */
680 __u64 relocs_ptr;
681
682 /** Required alignment in graphics aperture */
683 __u64 alignment;
684
685 /**
686 * When the EXEC_OBJECT_PINNED flag is specified this is populated by
687 * the user with the GTT offset at which this object will be pinned.
688 * When the I915_EXEC_NO_RELOC flag is specified this must contain the
689 * presumed_offset of the object.
690 * During execbuffer2 the kernel populates it with the value of the
691 * current GTT offset of the object, for future presumed_offset writes.
692 */
693 __u64 offset;
694
695#define EXEC_OBJECT_NEEDS_FENCE (1<<0)
696#define EXEC_OBJECT_NEEDS_GTT (1<<1)
697#define EXEC_OBJECT_WRITE (1<<2)
698#define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3)
699#define EXEC_OBJECT_PINNED (1<<4)
700#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_PINNED<<1)
701 __u64 flags;
702
703 __u64 rsvd1;
704 __u64 rsvd2;
705};
706
707struct drm_i915_gem_execbuffer2 {
708 /**
709 * List of gem_exec_object2 structs
710 */
711 __u64 buffers_ptr;
712 __u32 buffer_count;
713
714 /** Offset in the batchbuffer to start execution from. */
715 __u32 batch_start_offset;
716 /** Bytes used in batchbuffer from batch_start_offset */
717 __u32 batch_len;
718 __u32 DR1;
719 __u32 DR4;
720 __u32 num_cliprects;
721 /** This is a struct drm_clip_rect *cliprects */
722 __u64 cliprects_ptr;
723#define I915_EXEC_RING_MASK (7<<0)
724#define I915_EXEC_DEFAULT (0<<0)
725#define I915_EXEC_RENDER (1<<0)
726#define I915_EXEC_BSD (2<<0)
727#define I915_EXEC_BLT (3<<0)
728#define I915_EXEC_VEBOX (4<<0)
729
730/* Used for switching the constants addressing mode on gen4+ RENDER ring.
731 * Gen6+ only supports relative addressing to dynamic state (default) and
732 * absolute addressing.
733 *
734 * These flags are ignored for the BSD and BLT rings.
735 */
736#define I915_EXEC_CONSTANTS_MASK (3<<6)
737#define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */
738#define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6)
739#define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */
740 __u64 flags;
741 __u64 rsvd1; /* now used for context info */
742 __u64 rsvd2;
743};
744
745/** Resets the SO write offset registers for transform feedback on gen7. */
746#define I915_EXEC_GEN7_SOL_RESET (1<<8)
747
748/** Request a privileged ("secure") batch buffer. Note only available for
749 * DRM_ROOT_ONLY | DRM_MASTER processes.
750 */
751#define I915_EXEC_SECURE (1<<9)
752
753/** Inform the kernel that the batch is and will always be pinned. This
754 * negates the requirement for a workaround to be performed to avoid
755 * an incoherent CS (such as can be found on 830/845). If this flag is
756 * not passed, the kernel will endeavour to make sure the batch is
757 * coherent with the CS before execution. If this flag is passed,
758 * userspace assumes the responsibility for ensuring the same.
759 */
760#define I915_EXEC_IS_PINNED (1<<10)
761
762/** Provide a hint to the kernel that the command stream and auxiliary
763 * state buffers already holds the correct presumed addresses and so the
764 * relocation process may be skipped if no buffers need to be moved in
765 * preparation for the execbuffer.
766 */
767#define I915_EXEC_NO_RELOC (1<<11)
768
769/** Use the reloc.handle as an index into the exec object array rather
770 * than as the per-file handle.
771 */
772#define I915_EXEC_HANDLE_LUT (1<<12)
773
774/** Used for switching BSD rings on the platforms with two BSD rings */
775#define I915_EXEC_BSD_MASK (3<<13)
776#define I915_EXEC_BSD_DEFAULT (0<<13) /* default ping-pong mode */
777#define I915_EXEC_BSD_RING1 (1<<13)
778#define I915_EXEC_BSD_RING2 (2<<13)
779
780/** Tell the kernel that the batchbuffer is processed by
781 * the resource streamer.
782 */
783#define I915_EXEC_RESOURCE_STREAMER (1<<15)
784
785#define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_RESOURCE_STREAMER<<1)
786
787#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
788#define i915_execbuffer2_set_context_id(eb2, context) \
789 (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK
790#define i915_execbuffer2_get_context_id(eb2) \
791 ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK)
792
793struct drm_i915_gem_pin {
794 /** Handle of the buffer to be pinned. */
795 __u32 handle;
796 __u32 pad;
797
798 /** alignment required within the aperture */
799 __u64 alignment;
800
801 /** Returned GTT offset of the buffer. */
802 __u64 offset;
803};
804
805struct drm_i915_gem_unpin {
806 /** Handle of the buffer to be unpinned. */
807 __u32 handle;
808 __u32 pad;
809};
810
811struct drm_i915_gem_busy {
812 /** Handle of the buffer to check for busy */
813 __u32 handle;
814
815 /** Return busy status (1 if busy, 0 if idle).
816 * The high word is used to indicate on which rings the object
817 * currently resides:
818 * 16:31 - busy (r or r/w) rings (16 render, 17 bsd, 18 blt, etc)
819 */
820 __u32 busy;
821};
822
823/**
824 * I915_CACHING_NONE
825 *
826 * GPU access is not coherent with cpu caches. Default for machines without an
827 * LLC.
828 */
829#define I915_CACHING_NONE 0
830/**
831 * I915_CACHING_CACHED
832 *
833 * GPU access is coherent with cpu caches and furthermore the data is cached in
834 * last-level caches shared between cpu cores and the gpu GT. Default on
835 * machines with HAS_LLC.
836 */
837#define I915_CACHING_CACHED 1
838/**
839 * I915_CACHING_DISPLAY
840 *
841 * Special GPU caching mode which is coherent with the scanout engines.
842 * Transparently falls back to I915_CACHING_NONE on platforms where no special
843 * cache mode (like write-through or gfdt flushing) is available. The kernel
844 * automatically sets this mode when using a buffer as a scanout target.
845 * Userspace can manually set this mode to avoid a costly stall and clflush in
846 * the hotpath of drawing the first frame.
847 */
848#define I915_CACHING_DISPLAY 2
849
850struct drm_i915_gem_caching {
851 /**
852 * Handle of the buffer to set/get the caching level of. */
853 __u32 handle;
854
855 /**
856 * Cacheing level to apply or return value
857 *
858 * bits0-15 are for generic caching control (i.e. the above defined
859 * values). bits16-31 are reserved for platform-specific variations
860 * (e.g. l3$ caching on gen7). */
861 __u32 caching;
862};
863
864#define I915_TILING_NONE 0
865#define I915_TILING_X 1
866#define I915_TILING_Y 2
867
868#define I915_BIT_6_SWIZZLE_NONE 0
869#define I915_BIT_6_SWIZZLE_9 1
870#define I915_BIT_6_SWIZZLE_9_10 2
871#define I915_BIT_6_SWIZZLE_9_11 3
872#define I915_BIT_6_SWIZZLE_9_10_11 4
873/* Not seen by userland */
874#define I915_BIT_6_SWIZZLE_UNKNOWN 5
875/* Seen by userland. */
876#define I915_BIT_6_SWIZZLE_9_17 6
877#define I915_BIT_6_SWIZZLE_9_10_17 7
878
879struct drm_i915_gem_set_tiling {
880 /** Handle of the buffer to have its tiling state updated */
881 __u32 handle;
882
883 /**
884 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
885 * I915_TILING_Y).
886 *
887 * This value is to be set on request, and will be updated by the
888 * kernel on successful return with the actual chosen tiling layout.
889 *
890 * The tiling mode may be demoted to I915_TILING_NONE when the system
891 * has bit 6 swizzling that can't be managed correctly by GEM.
892 *
893 * Buffer contents become undefined when changing tiling_mode.
894 */
895 __u32 tiling_mode;
896
897 /**
898 * Stride in bytes for the object when in I915_TILING_X or
899 * I915_TILING_Y.
900 */
901 __u32 stride;
902
903 /**
904 * Returned address bit 6 swizzling required for CPU access through
905 * mmap mapping.
906 */
907 __u32 swizzle_mode;
908};
909
910struct drm_i915_gem_get_tiling {
911 /** Handle of the buffer to get tiling state for. */
912 __u32 handle;
913
914 /**
915 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
916 * I915_TILING_Y).
917 */
918 __u32 tiling_mode;
919
920 /**
921 * Returned address bit 6 swizzling required for CPU access through
922 * mmap mapping.
923 */
924 __u32 swizzle_mode;
925
926 /**
927 * Returned address bit 6 swizzling required for CPU access through
928 * mmap mapping whilst bound.
929 */
930 __u32 phys_swizzle_mode;
931};
932
933struct drm_i915_gem_get_aperture {
934 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */
935 __u64 aper_size;
936
937 /**
938 * Available space in the aperture used by i915_gem_execbuffer, in
939 * bytes
940 */
941 __u64 aper_available_size;
942};
943
944struct drm_i915_get_pipe_from_crtc_id {
945 /** ID of CRTC being requested **/
946 __u32 crtc_id;
947
948 /** pipe of requested CRTC **/
949 __u32 pipe;
950};
951
952#define I915_MADV_WILLNEED 0
953#define I915_MADV_DONTNEED 1
954#define __I915_MADV_PURGED 2 /* internal state */
955
956struct drm_i915_gem_madvise {
957 /** Handle of the buffer to change the backing store advice */
958 __u32 handle;
959
960 /* Advice: either the buffer will be needed again in the near future,
961 * or wont be and could be discarded under memory pressure.
962 */
963 __u32 madv;
964
965 /** Whether the backing store still exists. */
966 __u32 retained;
967};
968
969/* flags */
970#define I915_OVERLAY_TYPE_MASK 0xff
971#define I915_OVERLAY_YUV_PLANAR 0x01
972#define I915_OVERLAY_YUV_PACKED 0x02
973#define I915_OVERLAY_RGB 0x03
974
975#define I915_OVERLAY_DEPTH_MASK 0xff00
976#define I915_OVERLAY_RGB24 0x1000
977#define I915_OVERLAY_RGB16 0x2000
978#define I915_OVERLAY_RGB15 0x3000
979#define I915_OVERLAY_YUV422 0x0100
980#define I915_OVERLAY_YUV411 0x0200
981#define I915_OVERLAY_YUV420 0x0300
982#define I915_OVERLAY_YUV410 0x0400
983
984#define I915_OVERLAY_SWAP_MASK 0xff0000
985#define I915_OVERLAY_NO_SWAP 0x000000
986#define I915_OVERLAY_UV_SWAP 0x010000
987#define I915_OVERLAY_Y_SWAP 0x020000
988#define I915_OVERLAY_Y_AND_UV_SWAP 0x030000
989
990#define I915_OVERLAY_FLAGS_MASK 0xff000000
991#define I915_OVERLAY_ENABLE 0x01000000
992
993struct drm_intel_overlay_put_image {
994 /* various flags and src format description */
995 __u32 flags;
996 /* source picture description */
997 __u32 bo_handle;
998 /* stride values and offsets are in bytes, buffer relative */
999 __u16 stride_Y; /* stride for packed formats */
1000 __u16 stride_UV;
1001 __u32 offset_Y; /* offset for packet formats */
1002 __u32 offset_U;
1003 __u32 offset_V;
1004 /* in pixels */
1005 __u16 src_width;
1006 __u16 src_height;
1007 /* to compensate the scaling factors for partially covered surfaces */
1008 __u16 src_scan_width;
1009 __u16 src_scan_height;
1010 /* output crtc description */
1011 __u32 crtc_id;
1012 __u16 dst_x;
1013 __u16 dst_y;
1014 __u16 dst_width;
1015 __u16 dst_height;
1016};
1017
1018/* flags */
1019#define I915_OVERLAY_UPDATE_ATTRS (1<<0)
1020#define I915_OVERLAY_UPDATE_GAMMA (1<<1)
1021#define I915_OVERLAY_DISABLE_DEST_COLORKEY (1<<2)
1022struct drm_intel_overlay_attrs {
1023 __u32 flags;
1024 __u32 color_key;
1025 __s32 brightness;
1026 __u32 contrast;
1027 __u32 saturation;
1028 __u32 gamma0;
1029 __u32 gamma1;
1030 __u32 gamma2;
1031 __u32 gamma3;
1032 __u32 gamma4;
1033 __u32 gamma5;
1034};
1035
1036/*
1037 * Intel sprite handling
1038 *
1039 * Color keying works with a min/mask/max tuple. Both source and destination
1040 * color keying is allowed.
1041 *
1042 * Source keying:
1043 * Sprite pixels within the min & max values, masked against the color channels
1044 * specified in the mask field, will be transparent. All other pixels will
1045 * be displayed on top of the primary plane. For RGB surfaces, only the min
1046 * and mask fields will be used; ranged compares are not allowed.
1047 *
1048 * Destination keying:
1049 * Primary plane pixels that match the min value, masked against the color
1050 * channels specified in the mask field, will be replaced by corresponding
1051 * pixels from the sprite plane.
1052 *
1053 * Note that source & destination keying are exclusive; only one can be
1054 * active on a given plane.
1055 */
1056
1057#define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */
1058#define I915_SET_COLORKEY_DESTINATION (1<<1)
1059#define I915_SET_COLORKEY_SOURCE (1<<2)
1060struct drm_intel_sprite_colorkey {
1061 __u32 plane_id;
1062 __u32 min_value;
1063 __u32 channel_mask;
1064 __u32 max_value;
1065 __u32 flags;
1066};
1067
1068struct drm_i915_gem_wait {
1069 /** Handle of BO we shall wait on */
1070 __u32 bo_handle;
1071 __u32 flags;
1072 /** Number of nanoseconds to wait, Returns time remaining. */
1073 __s64 timeout_ns;
1074};
1075
1076struct drm_i915_gem_context_create {
1077 /* output: id of new context*/
1078 __u32 ctx_id;
1079 __u32 pad;
1080};
1081
1082struct drm_i915_gem_context_destroy {
1083 __u32 ctx_id;
1084 __u32 pad;
1085};
1086
1087struct drm_i915_reg_read {
1088 /*
1089 * Register offset.
1090 * For 64bit wide registers where the upper 32bits don't immediately
1091 * follow the lower 32bits, the offset of the lower 32bits must
1092 * be specified
1093 */
1094 __u64 offset;
1095 __u64 val; /* Return value */
1096};
1097/* Known registers:
1098 *
1099 * Render engine timestamp - 0x2358 + 64bit - gen7+
1100 * - Note this register returns an invalid value if using the default
1101 * single instruction 8byte read, in order to workaround that use
1102 * offset (0x2538 | 1) instead.
1103 *
1104 */
1105
1106struct drm_i915_reset_stats {
1107 __u32 ctx_id;
1108 __u32 flags;
1109
1110 /* All resets since boot/module reload, for all contexts */
1111 __u32 reset_count;
1112
1113 /* Number of batches lost when active in GPU, for this context */
1114 __u32 batch_active;
1115
1116 /* Number of batches lost pending for execution, for this context */
1117 __u32 batch_pending;
1118
1119 __u32 pad;
1120};
1121
1122struct drm_i915_gem_userptr {
1123 __u64 user_ptr;
1124 __u64 user_size;
1125 __u32 flags;
1126#define I915_USERPTR_READ_ONLY 0x1
1127#define I915_USERPTR_UNSYNCHRONIZED 0x80000000
1128 /**
1129 * Returned handle for the object.
1130 *
1131 * Object handles are nonzero.
1132 */
1133 __u32 handle;
1134};
1135
1136struct drm_i915_gem_context_param {
1137 __u32 ctx_id;
1138 __u32 size;
1139 __u64 param;
1140#define I915_CONTEXT_PARAM_BAN_PERIOD 0x1
1141#define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2
1142#define I915_CONTEXT_PARAM_GTT_SIZE 0x3
1143 __u64 value;
1144};
1145
1146#endif /* _I915_DRM_H_ */
diff --git a/src/static_libs/libdrm/intel_bufmgr.h b/src/static_libs/libdrm/intel_bufmgr.h
new file mode 100644
index 0000000000..a1abbcd2b0
--- /dev/null
+++ b/src/static_libs/libdrm/intel_bufmgr.h
@@ -0,0 +1,321 @@
1/*
2 * Copyright © 2008-2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28/**
29 * @file intel_bufmgr.h
30 *
31 * Public definitions of Intel-specific bufmgr functions.
32 */
33
34#ifndef INTEL_BUFMGR_H
35#define INTEL_BUFMGR_H
36
37#include <stdio.h>
38#include <stdint.h>
39#include <stdio.h>
40
41#if defined(__cplusplus)
42extern "C" {
43#endif
44
45struct drm_clip_rect;
46
47typedef struct _drm_intel_bufmgr drm_intel_bufmgr;
48typedef struct _drm_intel_context drm_intel_context;
49typedef struct _drm_intel_bo drm_intel_bo;
50
51struct _drm_intel_bo {
52 /**
53 * Size in bytes of the buffer object.
54 *
55 * The size may be larger than the size originally requested for the
56 * allocation, such as being aligned to page size.
57 */
58 unsigned long size;
59
60 /**
61 * Alignment requirement for object
62 *
63 * Used for GTT mapping & pinning the object.
64 */
65 unsigned long align;
66
67 /**
68 * Deprecated field containing (possibly the low 32-bits of) the last
69 * seen virtual card address. Use offset64 instead.
70 */
71 unsigned long offset;
72
73 /**
74 * Virtual address for accessing the buffer data. Only valid while
75 * mapped.
76 */
77#ifdef __cplusplus
78 void *virt;
79#else
80 void *virtual;
81#endif
82
83 /** Buffer manager context associated with this buffer object */
84 drm_intel_bufmgr *bufmgr;
85
86 /**
87 * MM-specific handle for accessing object
88 */
89 int handle;
90
91 /**
92 * Last seen card virtual address (offset from the beginning of the
93 * aperture) for the object. This should be used to fill relocation
94 * entries when calling drm_intel_bo_emit_reloc()
95 */
96 uint64_t offset64;
97};
98
99enum aub_dump_bmp_format {
100 AUB_DUMP_BMP_FORMAT_8BIT = 1,
101 AUB_DUMP_BMP_FORMAT_ARGB_4444 = 4,
102 AUB_DUMP_BMP_FORMAT_ARGB_0888 = 6,
103 AUB_DUMP_BMP_FORMAT_ARGB_8888 = 7,
104};
105
106typedef struct _drm_intel_aub_annotation {
107 uint32_t type;
108 uint32_t subtype;
109 uint32_t ending_offset;
110} drm_intel_aub_annotation;
111
112#define BO_ALLOC_FOR_RENDER (1<<0)
113
114drm_intel_bo *drm_intel_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name,
115 unsigned long size, unsigned int alignment);
116drm_intel_bo *drm_intel_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
117 const char *name,
118 unsigned long size,
119 unsigned int alignment);
120drm_intel_bo *drm_intel_bo_alloc_userptr(drm_intel_bufmgr *bufmgr,
121 const char *name,
122 void *addr, uint32_t tiling_mode,
123 uint32_t stride, unsigned long size,
124 unsigned long flags);
125drm_intel_bo *drm_intel_bo_alloc_tiled(drm_intel_bufmgr *bufmgr,
126 const char *name,
127 int x, int y, int cpp,
128 uint32_t *tiling_mode,
129 unsigned long *pitch,
130 unsigned long flags);
131void drm_intel_bo_reference(drm_intel_bo *bo);
132void drm_intel_bo_unreference(drm_intel_bo *bo);
133int drm_intel_bo_map(drm_intel_bo *bo, int write_enable);
134int drm_intel_bo_unmap(drm_intel_bo *bo);
135
136int drm_intel_bo_subdata(drm_intel_bo *bo, unsigned long offset,
137 unsigned long size, const void *data);
138int drm_intel_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
139 unsigned long size, void *data);
140void drm_intel_bo_wait_rendering(drm_intel_bo *bo);
141
142void drm_intel_bufmgr_set_debug(drm_intel_bufmgr *bufmgr, int enable_debug);
143void drm_intel_bufmgr_destroy(drm_intel_bufmgr *bufmgr);
144int drm_intel_bo_exec(drm_intel_bo *bo, int used,
145 struct drm_clip_rect *cliprects, int num_cliprects, int DR4);
146int drm_intel_bo_mrb_exec(drm_intel_bo *bo, int used,
147 struct drm_clip_rect *cliprects, int num_cliprects, int DR4,
148 unsigned int flags);
149int drm_intel_bufmgr_check_aperture_space(drm_intel_bo ** bo_array, int count);
150
151int drm_intel_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
152 drm_intel_bo *target_bo, uint32_t target_offset,
153 uint32_t read_domains, uint32_t write_domain);
154int drm_intel_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
155 drm_intel_bo *target_bo,
156 uint32_t target_offset,
157 uint32_t read_domains, uint32_t write_domain);
158int drm_intel_bo_pin(drm_intel_bo *bo, uint32_t alignment);
159int drm_intel_bo_unpin(drm_intel_bo *bo);
160int drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
161 uint32_t stride);
162int drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
163 uint32_t * swizzle_mode);
164int drm_intel_bo_flink(drm_intel_bo *bo, uint32_t * name);
165int drm_intel_bo_busy(drm_intel_bo *bo);
166int drm_intel_bo_madvise(drm_intel_bo *bo, int madv);
167int drm_intel_bo_use_48b_address_range(drm_intel_bo *bo, uint32_t enable);
168int drm_intel_bo_set_softpin_offset(drm_intel_bo *bo, uint64_t offset);
169
170int drm_intel_bo_disable_reuse(drm_intel_bo *bo);
171int drm_intel_bo_is_reusable(drm_intel_bo *bo);
172int drm_intel_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo);
173
174/* drm_intel_bufmgr_gem.c */
175drm_intel_bufmgr *drm_intel_bufmgr_gem_init(int fd, int batch_size);
176drm_intel_bo *drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
177 const char *name,
178 unsigned int handle);
179void drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr);
180void drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr);
181void drm_intel_bufmgr_gem_set_vma_cache_size(drm_intel_bufmgr *bufmgr,
182 int limit);
183int drm_intel_gem_bo_map_unsynchronized(drm_intel_bo *bo);
184int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo);
185int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo);
186
187int drm_intel_gem_bo_get_reloc_count(drm_intel_bo *bo);
188void drm_intel_gem_bo_clear_relocs(drm_intel_bo *bo, int start);
189void drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable);
190
191void
192drm_intel_bufmgr_gem_set_aub_filename(drm_intel_bufmgr *bufmgr,
193 const char *filename);
194void drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable);
195void drm_intel_gem_bo_aub_dump_bmp(drm_intel_bo *bo,
196 int x1, int y1, int width, int height,
197 enum aub_dump_bmp_format format,
198 int pitch, int offset);
199void
200drm_intel_bufmgr_gem_set_aub_annotations(drm_intel_bo *bo,
201 drm_intel_aub_annotation *annotations,
202 unsigned count);
203
204int drm_intel_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id);
205
206int drm_intel_get_aperture_sizes(int fd, size_t *mappable, size_t *total);
207int drm_intel_bufmgr_gem_get_devid(drm_intel_bufmgr *bufmgr);
208int drm_intel_gem_bo_wait(drm_intel_bo *bo, int64_t timeout_ns);
209
210drm_intel_context *drm_intel_gem_context_create(drm_intel_bufmgr *bufmgr);
211void drm_intel_gem_context_destroy(drm_intel_context *ctx);
212int drm_intel_gem_bo_context_exec(drm_intel_bo *bo, drm_intel_context *ctx,
213 int used, unsigned int flags);
214
215int drm_intel_bo_gem_export_to_prime(drm_intel_bo *bo, int *prime_fd);
216drm_intel_bo *drm_intel_bo_gem_create_from_prime(drm_intel_bufmgr *bufmgr,
217 int prime_fd, int size);
218
219/* drm_intel_bufmgr_fake.c */
220drm_intel_bufmgr *drm_intel_bufmgr_fake_init(int fd,
221 unsigned long low_offset,
222 void *low_virtual,
223 unsigned long size,
224 volatile unsigned int
225 *last_dispatch);
226void drm_intel_bufmgr_fake_set_last_dispatch(drm_intel_bufmgr *bufmgr,
227 volatile unsigned int
228 *last_dispatch);
229void drm_intel_bufmgr_fake_set_exec_callback(drm_intel_bufmgr *bufmgr,
230 int (*exec) (drm_intel_bo *bo,
231 unsigned int used,
232 void *priv),
233 void *priv);
234void drm_intel_bufmgr_fake_set_fence_callback(drm_intel_bufmgr *bufmgr,
235 unsigned int (*emit) (void *priv),
236 void (*wait) (unsigned int fence,
237 void *priv),
238 void *priv);
239drm_intel_bo *drm_intel_bo_fake_alloc_static(drm_intel_bufmgr *bufmgr,
240 const char *name,
241 unsigned long offset,
242 unsigned long size, void *virt);
243void drm_intel_bo_fake_disable_backing_store(drm_intel_bo *bo,
244 void (*invalidate_cb) (drm_intel_bo
245 * bo,
246 void *ptr),
247 void *ptr);
248
249void drm_intel_bufmgr_fake_contended_lock_take(drm_intel_bufmgr *bufmgr);
250void drm_intel_bufmgr_fake_evict_all(drm_intel_bufmgr *bufmgr);
251
252struct drm_intel_decode *drm_intel_decode_context_alloc(uint32_t devid);
253void drm_intel_decode_context_free(struct drm_intel_decode *ctx);
254void drm_intel_decode_set_batch_pointer(struct drm_intel_decode *ctx,
255 void *data, uint32_t hw_offset,
256 int count);
257void drm_intel_decode_set_dump_past_end(struct drm_intel_decode *ctx,
258 int dump_past_end);
259void drm_intel_decode_set_head_tail(struct drm_intel_decode *ctx,
260 uint32_t head, uint32_t tail);
261void drm_intel_decode_set_output_file(struct drm_intel_decode *ctx, FILE *out);
262void drm_intel_decode(struct drm_intel_decode *ctx);
263
264int drm_intel_reg_read(drm_intel_bufmgr *bufmgr,
265 uint32_t offset,
266 uint64_t *result);
267
268int drm_intel_get_reset_stats(drm_intel_context *ctx,
269 uint32_t *reset_count,
270 uint32_t *active,
271 uint32_t *pending);
272
273int drm_intel_get_subslice_total(int fd, unsigned int *subslice_total);
274int drm_intel_get_eu_total(int fd, unsigned int *eu_total);
275
276/** @{ Compatibility defines to keep old code building despite the symbol rename
277 * from dri_* to drm_intel_*
278 */
279#define dri_bo drm_intel_bo
280#define dri_bufmgr drm_intel_bufmgr
281#define dri_bo_alloc drm_intel_bo_alloc
282#define dri_bo_reference drm_intel_bo_reference
283#define dri_bo_unreference drm_intel_bo_unreference
284#define dri_bo_map drm_intel_bo_map
285#define dri_bo_unmap drm_intel_bo_unmap
286#define dri_bo_subdata drm_intel_bo_subdata
287#define dri_bo_get_subdata drm_intel_bo_get_subdata
288#define dri_bo_wait_rendering drm_intel_bo_wait_rendering
289#define dri_bufmgr_set_debug drm_intel_bufmgr_set_debug
290#define dri_bufmgr_destroy drm_intel_bufmgr_destroy
291#define dri_bo_exec drm_intel_bo_exec
292#define dri_bufmgr_check_aperture_space drm_intel_bufmgr_check_aperture_space
293#define dri_bo_emit_reloc(reloc_bo, read, write, target_offset, \
294 reloc_offset, target_bo) \
295 drm_intel_bo_emit_reloc(reloc_bo, reloc_offset, \
296 target_bo, target_offset, \
297 read, write);
298#define dri_bo_pin drm_intel_bo_pin
299#define dri_bo_unpin drm_intel_bo_unpin
300#define dri_bo_get_tiling drm_intel_bo_get_tiling
301#define dri_bo_set_tiling(bo, mode) drm_intel_bo_set_tiling(bo, mode, 0)
302#define dri_bo_flink drm_intel_bo_flink
303#define intel_bufmgr_gem_init drm_intel_bufmgr_gem_init
304#define intel_bo_gem_create_from_name drm_intel_bo_gem_create_from_name
305#define intel_bufmgr_gem_enable_reuse drm_intel_bufmgr_gem_enable_reuse
306#define intel_bufmgr_fake_init drm_intel_bufmgr_fake_init
307#define intel_bufmgr_fake_set_last_dispatch drm_intel_bufmgr_fake_set_last_dispatch
308#define intel_bufmgr_fake_set_exec_callback drm_intel_bufmgr_fake_set_exec_callback
309#define intel_bufmgr_fake_set_fence_callback drm_intel_bufmgr_fake_set_fence_callback
310#define intel_bo_fake_alloc_static drm_intel_bo_fake_alloc_static
311#define intel_bo_fake_disable_backing_store drm_intel_bo_fake_disable_backing_store
312#define intel_bufmgr_fake_contended_lock_take drm_intel_bufmgr_fake_contended_lock_take
313#define intel_bufmgr_fake_evict_all drm_intel_bufmgr_fake_evict_all
314
315/** @{ */
316
317#if defined(__cplusplus)
318}
319#endif
320
321#endif /* INTEL_BUFMGR_H */