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authorChris Michael <cp.michael@samsung.com>2017-06-09 14:23:57 -0400
committerChris Michael <cp.michael@samsung.com>2017-06-09 14:23:57 -0400
commitca66a9fa0de567086fc2c1405ca1980357a88db1 (patch)
tree732c4a6adbc2e89aa613ea4c8671191886dc7927 /src/static_libs
parent11fd8259ba5aa8835ce610d7de8d695168473dac (diff)
static_libs/libdrm: Update static libdrm headers
This patch updates our static_libs/libdrm header files to version 2.4.81-1 (from arch). NB: derek, I don't have the exynos headers here. Please update them when you can. Signed-off-by: Chris Michael <cp.michael@samsung.com>
Diffstat (limited to 'src/static_libs')
-rw-r--r--src/static_libs/libdrm/drm.h88
-rw-r--r--src/static_libs/libdrm/drm_fourcc.h17
-rw-r--r--src/static_libs/libdrm/drm_mode.h262
-rw-r--r--src/static_libs/libdrm/i915_drm.h315
-rw-r--r--src/static_libs/libdrm/intel_bufmgr.h20
5 files changed, 588 insertions, 114 deletions
diff --git a/src/static_libs/libdrm/drm.h b/src/static_libs/libdrm/drm.h
index a950b58..1e7a4bc 100644
--- a/src/static_libs/libdrm/drm.h
+++ b/src/static_libs/libdrm/drm.h
@@ -36,7 +36,7 @@
36#ifndef _DRM_H_ 36#ifndef _DRM_H_
37#define _DRM_H_ 37#define _DRM_H_
38 38
39#if defined(__linux__) 39#if defined(__linux__)
40 40
41#include <linux/types.h> 41#include <linux/types.h>
42#include <asm/ioctl.h> 42#include <asm/ioctl.h>
@@ -54,10 +54,15 @@ typedef int32_t __s32;
54typedef uint32_t __u32; 54typedef uint32_t __u32;
55typedef int64_t __s64; 55typedef int64_t __s64;
56typedef uint64_t __u64; 56typedef uint64_t __u64;
57typedef size_t __kernel_size_t;
57typedef unsigned long drm_handle_t; 58typedef unsigned long drm_handle_t;
58 59
59#endif 60#endif
60 61
62#if defined(__cplusplus)
63extern "C" {
64#endif
65
61#define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */ 66#define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */
62#define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */ 67#define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */
63#define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */ 68#define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */
@@ -129,11 +134,11 @@ struct drm_version {
129 int version_major; /**< Major version */ 134 int version_major; /**< Major version */
130 int version_minor; /**< Minor version */ 135 int version_minor; /**< Minor version */
131 int version_patchlevel; /**< Patch level */ 136 int version_patchlevel; /**< Patch level */
132 size_t name_len; /**< Length of name buffer */ 137 __kernel_size_t name_len; /**< Length of name buffer */
133 char *name; /**< Name of driver */ 138 char *name; /**< Name of driver */
134 size_t date_len; /**< Length of date buffer */ 139 __kernel_size_t date_len; /**< Length of date buffer */
135 char *date; /**< User-space buffer to hold date */ 140 char *date; /**< User-space buffer to hold date */
136 size_t desc_len; /**< Length of desc buffer */ 141 __kernel_size_t desc_len; /**< Length of desc buffer */
137 char *desc; /**< User-space buffer to hold desc */ 142 char *desc; /**< User-space buffer to hold desc */
138}; 143};
139 144
@@ -143,7 +148,7 @@ struct drm_version {
143 * \sa drmGetBusid() and drmSetBusId(). 148 * \sa drmGetBusid() and drmSetBusId().
144 */ 149 */
145struct drm_unique { 150struct drm_unique {
146 size_t unique_len; /**< Length of unique */ 151 __kernel_size_t unique_len; /**< Length of unique */
147 char *unique; /**< Unique name for driver instantiation */ 152 char *unique; /**< Unique name for driver instantiation */
148}; 153};
149 154
@@ -180,8 +185,7 @@ enum drm_map_type {
180 _DRM_SHM = 2, /**< shared, cached */ 185 _DRM_SHM = 2, /**< shared, cached */
181 _DRM_AGP = 3, /**< AGP/GART */ 186 _DRM_AGP = 3, /**< AGP/GART */
182 _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */ 187 _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */
183 _DRM_CONSISTENT = 5, /**< Consistent memory for PCI DMA */ 188 _DRM_CONSISTENT = 5 /**< Consistent memory for PCI DMA */
184 _DRM_GEM = 6 /**< GEM object */
185}; 189};
186 190
187/** 191/**
@@ -467,12 +471,15 @@ struct drm_irq_busid {
467enum drm_vblank_seq_type { 471enum drm_vblank_seq_type {
468 _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */ 472 _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */
469 _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */ 473 _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */
474 /* bits 1-6 are reserved for high crtcs */
475 _DRM_VBLANK_HIGH_CRTC_MASK = 0x0000003e,
470 _DRM_VBLANK_EVENT = 0x4000000, /**< Send event instead of blocking */ 476 _DRM_VBLANK_EVENT = 0x4000000, /**< Send event instead of blocking */
471 _DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */ 477 _DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */
472 _DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */ 478 _DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */
473 _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */ 479 _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */
474 _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking, unsupported */ 480 _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking, unsupported */
475}; 481};
482#define _DRM_VBLANK_HIGH_CRTC_SHIFT 1
476 483
477#define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE) 484#define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE)
478#define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_EVENT | _DRM_VBLANK_SIGNAL | \ 485#define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_EVENT | _DRM_VBLANK_SIGNAL | \
@@ -612,6 +619,30 @@ struct drm_gem_open {
612 __u64 size; 619 __u64 size;
613}; 620};
614 621
622#define DRM_CAP_DUMB_BUFFER 0x1
623#define DRM_CAP_VBLANK_HIGH_CRTC 0x2
624#define DRM_CAP_DUMB_PREFERRED_DEPTH 0x3
625#define DRM_CAP_DUMB_PREFER_SHADOW 0x4
626#define DRM_CAP_PRIME 0x5
627#define DRM_PRIME_CAP_IMPORT 0x1
628#define DRM_PRIME_CAP_EXPORT 0x2
629#define DRM_CAP_TIMESTAMP_MONOTONIC 0x6
630#define DRM_CAP_ASYNC_PAGE_FLIP 0x7
631/*
632 * The CURSOR_WIDTH and CURSOR_HEIGHT capabilities return a valid widthxheight
633 * combination for the hardware cursor. The intention is that a hardware
634 * agnostic userspace can query a cursor plane size to use.
635 *
636 * Note that the cross-driver contract is to merely return a valid size;
637 * drivers are free to attach another meaning on top, eg. i915 returns the
638 * maximum plane size.
639 */
640#define DRM_CAP_CURSOR_WIDTH 0x8
641#define DRM_CAP_CURSOR_HEIGHT 0x9
642#define DRM_CAP_ADDFB2_MODIFIERS 0x10
643#define DRM_CAP_PAGE_FLIP_TARGET 0x11
644#define DRM_CAP_CRTC_IN_VBLANK_EVENT 0x12
645
615/** DRM_IOCTL_GET_CAP ioctl argument type */ 646/** DRM_IOCTL_GET_CAP ioctl argument type */
616struct drm_get_cap { 647struct drm_get_cap {
617 __u64 capability; 648 __u64 capability;
@@ -630,17 +661,17 @@ struct drm_get_cap {
630/** 661/**
631 * DRM_CLIENT_CAP_UNIVERSAL_PLANES 662 * DRM_CLIENT_CAP_UNIVERSAL_PLANES
632 * 663 *
633 * if set to 1, the DRM core will expose the full universal plane list 664 * If set to 1, the DRM core will expose all planes (overlay, primary, and
634 * (including primary and cursor planes). 665 * cursor) to userspace.
635 */ 666 */
636#define DRM_CLIENT_CAP_UNIVERSAL_PLANES 2 667#define DRM_CLIENT_CAP_UNIVERSAL_PLANES 2
637 668
638/** 669/**
639 * DRM_CLIENT_CAP_ATOMIC 670 * DRM_CLIENT_CAP_ATOMIC
640 * 671 *
641 * If set to 1, the DRM core will allow atomic modesetting requests. 672 * If set to 1, the DRM core will expose atomic properties to userspace
642 */ 673 */
643#define DRM_CLIENT_CAP_ATOMIC 3 674#define DRM_CLIENT_CAP_ATOMIC 3
644 675
645/** DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */ 676/** DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */
646struct drm_set_client_cap { 677struct drm_set_client_cap {
@@ -648,6 +679,7 @@ struct drm_set_client_cap {
648 __u64 value; 679 __u64 value;
649}; 680};
650 681
682#define DRM_RDWR O_RDWR
651#define DRM_CLOEXEC O_CLOEXEC 683#define DRM_CLOEXEC O_CLOEXEC
652struct drm_prime_handle { 684struct drm_prime_handle {
653 __u32 handle; 685 __u32 handle;
@@ -659,8 +691,16 @@ struct drm_prime_handle {
659 __s32 fd; 691 __s32 fd;
660}; 692};
661 693
694#if defined(__cplusplus)
695}
696#endif
697
662#include "drm_mode.h" 698#include "drm_mode.h"
663 699
700#if defined(__cplusplus)
701extern "C" {
702#endif
703
664#define DRM_IOCTL_BASE 'd' 704#define DRM_IOCTL_BASE 'd'
665#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr) 705#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
666#define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type) 706#define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type)
@@ -743,8 +783,8 @@ struct drm_prime_handle {
743#define DRM_IOCTL_MODE_SETGAMMA DRM_IOWR(0xA5, struct drm_mode_crtc_lut) 783#define DRM_IOCTL_MODE_SETGAMMA DRM_IOWR(0xA5, struct drm_mode_crtc_lut)
744#define DRM_IOCTL_MODE_GETENCODER DRM_IOWR(0xA6, struct drm_mode_get_encoder) 784#define DRM_IOCTL_MODE_GETENCODER DRM_IOWR(0xA6, struct drm_mode_get_encoder)
745#define DRM_IOCTL_MODE_GETCONNECTOR DRM_IOWR(0xA7, struct drm_mode_get_connector) 785#define DRM_IOCTL_MODE_GETCONNECTOR DRM_IOWR(0xA7, struct drm_mode_get_connector)
746#define DRM_IOCTL_MODE_ATTACHMODE DRM_IOWR(0xA8, struct drm_mode_mode_cmd) 786#define DRM_IOCTL_MODE_ATTACHMODE DRM_IOWR(0xA8, struct drm_mode_mode_cmd) /* deprecated (never worked) */
747#define DRM_IOCTL_MODE_DETACHMODE DRM_IOWR(0xA9, struct drm_mode_mode_cmd) 787#define DRM_IOCTL_MODE_DETACHMODE DRM_IOWR(0xA9, struct drm_mode_mode_cmd) /* deprecated (never worked) */
748 788
749#define DRM_IOCTL_MODE_GETPROPERTY DRM_IOWR(0xAA, struct drm_mode_get_property) 789#define DRM_IOCTL_MODE_GETPROPERTY DRM_IOWR(0xAA, struct drm_mode_get_property)
750#define DRM_IOCTL_MODE_SETPROPERTY DRM_IOWR(0xAB, struct drm_mode_connector_set_property) 790#define DRM_IOCTL_MODE_SETPROPERTY DRM_IOWR(0xAB, struct drm_mode_connector_set_property)
@@ -771,7 +811,7 @@ struct drm_prime_handle {
771 811
772/** 812/**
773 * Device specific ioctls should only be in their respective headers 813 * Device specific ioctls should only be in their respective headers
774 * The device specific ioctl range is from 0x40 to 0x99. 814 * The device specific ioctl range is from 0x40 to 0x9f.
775 * Generic IOCTLS restart at 0xA0. 815 * Generic IOCTLS restart at 0xA0.
776 * 816 *
777 * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and 817 * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and
@@ -806,21 +846,9 @@ struct drm_event_vblank {
806 __u32 tv_sec; 846 __u32 tv_sec;
807 __u32 tv_usec; 847 __u32 tv_usec;
808 __u32 sequence; 848 __u32 sequence;
809 __u32 reserved; 849 __u32 crtc_id; /* 0 on older kernels that do not support this */
810}; 850};
811 851
812#define DRM_CAP_DUMB_BUFFER 0x1
813#define DRM_CAP_VBLANK_HIGH_CRTC 0x2
814#define DRM_CAP_DUMB_PREFERRED_DEPTH 0x3
815#define DRM_CAP_DUMB_PREFER_SHADOW 0x4
816#define DRM_CAP_PRIME 0x5
817#define DRM_CAP_TIMESTAMP_MONOTONIC 0x6
818#define DRM_CAP_ASYNC_PAGE_FLIP 0x7
819#define DRM_CAP_ADDFB2_MODIFIERS 0x10
820
821#define DRM_PRIME_CAP_IMPORT 0x1
822#define DRM_PRIME_CAP_EXPORT 0x2
823
824/* typedef area */ 852/* typedef area */
825typedef struct drm_clip_rect drm_clip_rect_t; 853typedef struct drm_clip_rect drm_clip_rect_t;
826typedef struct drm_drawable_info drm_drawable_info_t; 854typedef struct drm_drawable_info drm_drawable_info_t;
@@ -864,4 +892,8 @@ typedef struct drm_agp_info drm_agp_info_t;
864typedef struct drm_scatter_gather drm_scatter_gather_t; 892typedef struct drm_scatter_gather drm_scatter_gather_t;
865typedef struct drm_set_version drm_set_version_t; 893typedef struct drm_set_version drm_set_version_t;
866 894
895#if defined(__cplusplus)
896}
897#endif
898
867#endif 899#endif
diff --git a/src/static_libs/libdrm/drm_fourcc.h b/src/static_libs/libdrm/drm_fourcc.h
index e741b09..4d8da69 100644
--- a/src/static_libs/libdrm/drm_fourcc.h
+++ b/src/static_libs/libdrm/drm_fourcc.h
@@ -24,16 +24,23 @@
24#ifndef DRM_FOURCC_H 24#ifndef DRM_FOURCC_H
25#define DRM_FOURCC_H 25#define DRM_FOURCC_H
26 26
27#include <inttypes.h> 27#include "drm.h"
28 28
29#define fourcc_code(a,b,c,d) ((uint32_t)(a) | ((uint32_t)(b) << 8) | \ 29#define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \
30 ((uint32_t)(c) << 16) | ((uint32_t)(d) << 24)) 30 ((__u32)(c) << 16) | ((__u32)(d) << 24))
31 31
32#define DRM_FORMAT_BIG_ENDIAN (1<<31) /* format is big endian instead of little endian */ 32#define DRM_FORMAT_BIG_ENDIAN (1<<31) /* format is big endian instead of little endian */
33 33
34/* color index */ 34/* color index */
35#define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */ 35#define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
36 36
37/* 8 bpp Red */
38#define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */
39
40/* 16 bpp RG */
41#define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */
42#define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */
43
37/* 8 bpp RGB */ 44/* 8 bpp RGB */
38#define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */ 45#define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */
39#define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */ 46#define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */
@@ -106,6 +113,8 @@
106#define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */ 113#define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */
107#define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */ 114#define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */
108#define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */ 115#define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */
116#define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
117#define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
109 118
110/* 119/*
111 * 3 plane YCbCr 120 * 3 plane YCbCr
@@ -216,7 +225,7 @@
216 * - multiple of 128 pixels for the width 225 * - multiple of 128 pixels for the width
217 * - multiple of 32 pixels for the height 226 * - multiple of 32 pixels for the height
218 * 227 *
219 * For more information: see http://linuxtv.org/downloads/v4l-dvb-apis/re32.html 228 * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html
220 */ 229 */
221#define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1) 230#define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)
222 231
diff --git a/src/static_libs/libdrm/drm_mode.h b/src/static_libs/libdrm/drm_mode.h
index 115f36e..70571af 100644
--- a/src/static_libs/libdrm/drm_mode.h
+++ b/src/static_libs/libdrm/drm_mode.h
@@ -27,6 +27,12 @@
27#ifndef _DRM_MODE_H 27#ifndef _DRM_MODE_H
28#define _DRM_MODE_H 28#define _DRM_MODE_H
29 29
30#include "drm.h"
31
32#if defined(__cplusplus)
33extern "C" {
34#endif
35
30#define DRM_DISPLAY_INFO_LEN 32 36#define DRM_DISPLAY_INFO_LEN 32
31#define DRM_CONNECTOR_NAME_LEN 32 37#define DRM_CONNECTOR_NAME_LEN 32
32#define DRM_DISPLAY_MODE_LEN 32 38#define DRM_DISPLAY_MODE_LEN 32
@@ -41,7 +47,15 @@
41#define DRM_MODE_TYPE_DRIVER (1<<6) 47#define DRM_MODE_TYPE_DRIVER (1<<6)
42 48
43/* Video mode flags */ 49/* Video mode flags */
44/* bit compatible with the xorg definitions. */ 50/* bit compatible with the xrandr RR_ definitions (bits 0-13)
51 *
52 * ABI warning: Existing userspace really expects
53 * the mode flags to match the xrandr definitions. Any
54 * changes that don't match the xrandr definitions will
55 * likely need a new client cap or some other mechanism
56 * to avoid breaking existing userspace. This includes
57 * allocating new flags in the previously unused bits!
58 */
45#define DRM_MODE_FLAG_PHSYNC (1<<0) 59#define DRM_MODE_FLAG_PHSYNC (1<<0)
46#define DRM_MODE_FLAG_NHSYNC (1<<1) 60#define DRM_MODE_FLAG_NHSYNC (1<<1)
47#define DRM_MODE_FLAG_PVSYNC (1<<2) 61#define DRM_MODE_FLAG_PVSYNC (1<<2)
@@ -56,6 +70,10 @@
56#define DRM_MODE_FLAG_PIXMUX (1<<11) 70#define DRM_MODE_FLAG_PIXMUX (1<<11)
57#define DRM_MODE_FLAG_DBLCLK (1<<12) 71#define DRM_MODE_FLAG_DBLCLK (1<<12)
58#define DRM_MODE_FLAG_CLKDIV2 (1<<13) 72#define DRM_MODE_FLAG_CLKDIV2 (1<<13)
73 /*
74 * When adding a new stereo mode don't forget to adjust DRM_MODE_FLAGS_3D_MAX
75 * (define not exposed to user space).
76 */
59#define DRM_MODE_FLAG_3D_MASK (0x1f<<14) 77#define DRM_MODE_FLAG_3D_MASK (0x1f<<14)
60#define DRM_MODE_FLAG_3D_NONE (0<<14) 78#define DRM_MODE_FLAG_3D_NONE (0<<14)
61#define DRM_MODE_FLAG_3D_FRAME_PACKING (1<<14) 79#define DRM_MODE_FLAG_3D_FRAME_PACKING (1<<14)
@@ -82,6 +100,11 @@
82#define DRM_MODE_SCALE_CENTER 2 /* Centered, no scaling */ 100#define DRM_MODE_SCALE_CENTER 2 /* Centered, no scaling */
83#define DRM_MODE_SCALE_ASPECT 3 /* Full screen, preserve aspect */ 101#define DRM_MODE_SCALE_ASPECT 3 /* Full screen, preserve aspect */
84 102
103/* Picture aspect ratio options */
104#define DRM_MODE_PICTURE_ASPECT_NONE 0
105#define DRM_MODE_PICTURE_ASPECT_4_3 1
106#define DRM_MODE_PICTURE_ASPECT_16_9 2
107
85/* Dithering mode options */ 108/* Dithering mode options */
86#define DRM_MODE_DITHERING_OFF 0 109#define DRM_MODE_DITHERING_OFF 0
87#define DRM_MODE_DITHERING_ON 1 110#define DRM_MODE_DITHERING_ON 1
@@ -92,10 +115,22 @@
92#define DRM_MODE_DIRTY_ON 1 115#define DRM_MODE_DIRTY_ON 1
93#define DRM_MODE_DIRTY_ANNOTATE 2 116#define DRM_MODE_DIRTY_ANNOTATE 2
94 117
118/* Link Status options */
119#define DRM_MODE_LINK_STATUS_GOOD 0
120#define DRM_MODE_LINK_STATUS_BAD 1
121
95struct drm_mode_modeinfo { 122struct drm_mode_modeinfo {
96 __u32 clock; 123 __u32 clock;
97 __u16 hdisplay, hsync_start, hsync_end, htotal, hskew; 124 __u16 hdisplay;
98 __u16 vdisplay, vsync_start, vsync_end, vtotal, vscan; 125 __u16 hsync_start;
126 __u16 hsync_end;
127 __u16 htotal;
128 __u16 hskew;
129 __u16 vdisplay;
130 __u16 vsync_start;
131 __u16 vsync_end;
132 __u16 vtotal;
133 __u16 vscan;
99 134
100 __u32 vrefresh; 135 __u32 vrefresh;
101 136
@@ -113,8 +148,10 @@ struct drm_mode_card_res {
113 __u32 count_crtcs; 148 __u32 count_crtcs;
114 __u32 count_connectors; 149 __u32 count_connectors;
115 __u32 count_encoders; 150 __u32 count_encoders;
116 __u32 min_width, max_width; 151 __u32 min_width;
117 __u32 min_height, max_height; 152 __u32 max_width;
153 __u32 min_height;
154 __u32 max_height;
118}; 155};
119 156
120struct drm_mode_crtc { 157struct drm_mode_crtc {
@@ -124,30 +161,35 @@ struct drm_mode_crtc {
124 __u32 crtc_id; /**< Id */ 161 __u32 crtc_id; /**< Id */
125 __u32 fb_id; /**< Id of framebuffer */ 162 __u32 fb_id; /**< Id of framebuffer */
126 163
127 __u32 x, y; /**< Position on the frameuffer */ 164 __u32 x; /**< x Position on the framebuffer */
165 __u32 y; /**< y Position on the framebuffer */
128 166
129 __u32 gamma_size; 167 __u32 gamma_size;
130 __u32 mode_valid; 168 __u32 mode_valid;
131 struct drm_mode_modeinfo mode; 169 struct drm_mode_modeinfo mode;
132}; 170};
133 171
134#define DRM_MODE_PRESENT_TOP_FIELD (1<<0) 172#define DRM_MODE_PRESENT_TOP_FIELD (1<<0)
135#define DRM_MODE_PRESENT_BOTTOM_FIELD (1<<1) 173#define DRM_MODE_PRESENT_BOTTOM_FIELD (1<<1)
136 174
137/* Planes blend with or override other bits on the CRTC */ 175/* Planes blend with or override other bits on the CRTC */
138struct drm_mode_set_plane { 176struct drm_mode_set_plane {
139 __u32 plane_id; 177 __u32 plane_id;
140 __u32 crtc_id; 178 __u32 crtc_id;
141 __u32 fb_id; /* fb object contains surface format type */ 179 __u32 fb_id; /* fb object contains surface format type */
142 __u32 flags; 180 __u32 flags; /* see above flags */
143 181
144 /* Signed dest location allows it to be partially off screen */ 182 /* Signed dest location allows it to be partially off screen */
145 __s32 crtc_x, crtc_y; 183 __s32 crtc_x;
146 __u32 crtc_w, crtc_h; 184 __s32 crtc_y;
185 __u32 crtc_w;
186 __u32 crtc_h;
147 187
148 /* Source values are 16.16 fixed point */ 188 /* Source values are 16.16 fixed point */
149 __u32 src_x, src_y; 189 __u32 src_x;
150 __u32 src_h, src_w; 190 __u32 src_y;
191 __u32 src_h;
192 __u32 src_w;
151}; 193};
152 194
153struct drm_mode_get_plane { 195struct drm_mode_get_plane {
@@ -176,6 +218,7 @@ struct drm_mode_get_plane_res {
176#define DRM_MODE_ENCODER_VIRTUAL 5 218#define DRM_MODE_ENCODER_VIRTUAL 5
177#define DRM_MODE_ENCODER_DSI 6 219#define DRM_MODE_ENCODER_DSI 6
178#define DRM_MODE_ENCODER_DPMST 7 220#define DRM_MODE_ENCODER_DPMST 7
221#define DRM_MODE_ENCODER_DPI 8
179 222
180struct drm_mode_get_encoder { 223struct drm_mode_get_encoder {
181 __u32 encoder_id; 224 __u32 encoder_id;
@@ -189,14 +232,16 @@ struct drm_mode_get_encoder {
189 232
190/* This is for connectors with multiple signal types. */ 233/* This is for connectors with multiple signal types. */
191/* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */ 234/* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */
192#define DRM_MODE_SUBCONNECTOR_Automatic 0 235enum drm_mode_subconnector {
193#define DRM_MODE_SUBCONNECTOR_Unknown 0 236 DRM_MODE_SUBCONNECTOR_Automatic = 0,
194#define DRM_MODE_SUBCONNECTOR_DVID 3 237 DRM_MODE_SUBCONNECTOR_Unknown = 0,
195#define DRM_MODE_SUBCONNECTOR_DVIA 4 238 DRM_MODE_SUBCONNECTOR_DVID = 3,
196#define DRM_MODE_SUBCONNECTOR_Composite 5 239 DRM_MODE_SUBCONNECTOR_DVIA = 4,
197#define DRM_MODE_SUBCONNECTOR_SVIDEO 6 240 DRM_MODE_SUBCONNECTOR_Composite = 5,
198#define DRM_MODE_SUBCONNECTOR_Component 8 241 DRM_MODE_SUBCONNECTOR_SVIDEO = 6,
199#define DRM_MODE_SUBCONNECTOR_SCART 9 242 DRM_MODE_SUBCONNECTOR_Component = 8,
243 DRM_MODE_SUBCONNECTOR_SCART = 9,
244};
200 245
201#define DRM_MODE_CONNECTOR_Unknown 0 246#define DRM_MODE_CONNECTOR_Unknown 0
202#define DRM_MODE_CONNECTOR_VGA 1 247#define DRM_MODE_CONNECTOR_VGA 1
@@ -215,6 +260,7 @@ struct drm_mode_get_encoder {
215#define DRM_MODE_CONNECTOR_eDP 14 260#define DRM_MODE_CONNECTOR_eDP 14
216#define DRM_MODE_CONNECTOR_VIRTUAL 15 261#define DRM_MODE_CONNECTOR_VIRTUAL 15
217#define DRM_MODE_CONNECTOR_DSI 16 262#define DRM_MODE_CONNECTOR_DSI 16
263#define DRM_MODE_CONNECTOR_DPI 17
218 264
219struct drm_mode_get_connector { 265struct drm_mode_get_connector {
220 266
@@ -233,8 +279,11 @@ struct drm_mode_get_connector {
233 __u32 connector_type_id; 279 __u32 connector_type_id;
234 280
235 __u32 connection; 281 __u32 connection;
236 __u32 mm_width, mm_height; /**< HxW in millimeters */ 282 __u32 mm_width; /**< width in millimeters */
283 __u32 mm_height; /**< height in millimeters */
237 __u32 subpixel; 284 __u32 subpixel;
285
286 __u32 pad;
238}; 287};
239 288
240#define DRM_MODE_PROP_PENDING (1<<0) 289#define DRM_MODE_PROP_PENDING (1<<0)
@@ -259,6 +308,13 @@ struct drm_mode_get_connector {
259#define DRM_MODE_PROP_OBJECT DRM_MODE_PROP_TYPE(1) 308#define DRM_MODE_PROP_OBJECT DRM_MODE_PROP_TYPE(1)
260#define DRM_MODE_PROP_SIGNED_RANGE DRM_MODE_PROP_TYPE(2) 309#define DRM_MODE_PROP_SIGNED_RANGE DRM_MODE_PROP_TYPE(2)
261 310
311/* the PROP_ATOMIC flag is used to hide properties from userspace that
312 * is not aware of atomic properties. This is mostly to work around
313 * older userspace (DDX drivers) that read/write each prop they find,
314 * witout being aware that this could be triggering a lengthy modeset.
315 */
316#define DRM_MODE_PROP_ATOMIC 0x80000000
317
262struct drm_mode_property_enum { 318struct drm_mode_property_enum {
263 __u64 value; 319 __u64 value;
264 char name[DRM_PROP_NAME_LEN]; 320 char name[DRM_PROP_NAME_LEN];
@@ -273,6 +329,8 @@ struct drm_mode_get_property {
273 char name[DRM_PROP_NAME_LEN]; 329 char name[DRM_PROP_NAME_LEN];
274 330
275 __u32 count_values; 331 __u32 count_values;
332 /* This is only used to count enum values, not blobs. The _blobs is
333 * simply because of a historical reason, i.e. backwards compat. */
276 __u32 count_enum_blobs; 334 __u32 count_enum_blobs;
277}; 335};
278 336
@@ -290,6 +348,7 @@ struct drm_mode_connector_set_property {
290#define DRM_MODE_OBJECT_FB 0xfbfbfbfb 348#define DRM_MODE_OBJECT_FB 0xfbfbfbfb
291#define DRM_MODE_OBJECT_BLOB 0xbbbbbbbb 349#define DRM_MODE_OBJECT_BLOB 0xbbbbbbbb
292#define DRM_MODE_OBJECT_PLANE 0xeeeeeeee 350#define DRM_MODE_OBJECT_PLANE 0xeeeeeeee
351#define DRM_MODE_OBJECT_ANY 0
293 352
294struct drm_mode_obj_get_properties { 353struct drm_mode_obj_get_properties {
295 __u64 props_ptr; 354 __u64 props_ptr;
@@ -314,7 +373,8 @@ struct drm_mode_get_blob {
314 373
315struct drm_mode_fb_cmd { 374struct drm_mode_fb_cmd {
316 __u32 fb_id; 375 __u32 fb_id;
317 __u32 width, height; 376 __u32 width;
377 __u32 height;
318 __u32 pitch; 378 __u32 pitch;
319 __u32 bpp; 379 __u32 bpp;
320 __u32 depth; 380 __u32 depth;
@@ -327,9 +387,10 @@ struct drm_mode_fb_cmd {
327 387
328struct drm_mode_fb_cmd2 { 388struct drm_mode_fb_cmd2 {
329 __u32 fb_id; 389 __u32 fb_id;
330 __u32 width, height; 390 __u32 width;
391 __u32 height;
331 __u32 pixel_format; /* fourcc code from drm_fourcc.h */ 392 __u32 pixel_format; /* fourcc code from drm_fourcc.h */
332 __u32 flags; 393 __u32 flags; /* see above flags */
333 394
334 /* 395 /*
335 * In case of planar formats, this ioctl allows up to 4 396 * In case of planar formats, this ioctl allows up to 4
@@ -341,27 +402,32 @@ struct drm_mode_fb_cmd2 {
341 * followed by an interleaved U/V plane containing 402 * followed by an interleaved U/V plane containing
342 * 8 bit 2x2 subsampled colour difference samples. 403 * 8 bit 2x2 subsampled colour difference samples.
343 * 404 *
344 * So it would consist of Y as offset[0] and UV as 405 * So it would consist of Y as offsets[0] and UV as
345 * offset[1]. Note that offset[0] will generally 406 * offsets[1]. Note that offsets[0] will generally
346 * be 0. 407 * be 0 (but this is not required).
347 * 408 *
348 * To accommodate tiled, compressed, etc formats, a per-plane 409 * To accommodate tiled, compressed, etc formats, a
349 * modifier can be specified. The default value of zero 410 * modifier can be specified. The default value of zero
350 * indicates "native" format as specified by the fourcc. 411 * indicates "native" format as specified by the fourcc.
351 * Vendor specific modifier token. This allows, for example, 412 * Vendor specific modifier token. Note that even though
352 * different tiling/swizzling pattern on different planes. 413 * it looks like we have a modifier per-plane, we in fact
353 * See discussion above of DRM_FORMAT_MOD_xxx. 414 * do not. The modifier for each plane must be identical.
415 * Thus all combinations of different data layouts for
416 * multi plane formats must be enumerated as separate
417 * modifiers.
354 */ 418 */
355 __u32 handles[4]; 419 __u32 handles[4];
356 __u32 pitches[4]; /* pitch for each plane */ 420 __u32 pitches[4]; /* pitch for each plane */
357 __u32 offsets[4]; /* offset of each plane */ 421 __u32 offsets[4]; /* offset of each plane */
358 __u64 modifier[4]; /* ie, tiling, compressed (per plane) */ 422 __u64 modifier[4]; /* ie, tiling, compress */
359}; 423};
360 424
361#define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01 425#define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01
362#define DRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02 426#define DRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02
363#define DRM_MODE_FB_DIRTY_FLAGS 0x03 427#define DRM_MODE_FB_DIRTY_FLAGS 0x03
364 428
429#define DRM_MODE_FB_DIRTY_MAX_CLIPS 256
430
365/* 431/*
366 * Mark a region of a framebuffer as dirty. 432 * Mark a region of a framebuffer as dirty.
367 * 433 *
@@ -402,20 +468,21 @@ struct drm_mode_mode_cmd {
402 struct drm_mode_modeinfo mode; 468 struct drm_mode_modeinfo mode;
403}; 469};
404 470
405#define DRM_MODE_CURSOR_BO (1<<0) 471#define DRM_MODE_CURSOR_BO 0x01
406#define DRM_MODE_CURSOR_MOVE (1<<1) 472#define DRM_MODE_CURSOR_MOVE 0x02
473#define DRM_MODE_CURSOR_FLAGS 0x03
407 474
408/* 475/*
409 * depending on the value in flags diffrent members are used. 476 * depending on the value in flags different members are used.
410 * 477 *
411 * CURSOR_BO uses 478 * CURSOR_BO uses
412 * crtc 479 * crtc_id
413 * width 480 * width
414 * height 481 * height
415 * handle - if 0 turns the cursor of 482 * handle - if 0 turns the cursor off
416 * 483 *
417 * CURSOR_MOVE uses 484 * CURSOR_MOVE uses
418 * crtc 485 * crtc_id
419 * x 486 * x
420 * y 487 * y
421 */ 488 */
@@ -453,9 +520,30 @@ struct drm_mode_crtc_lut {
453 __u64 blue; 520 __u64 blue;
454}; 521};
455 522
523struct drm_color_ctm {
524 /* Conversion matrix in S31.32 format. */
525 __s64 matrix[9];
526};
527
528struct drm_color_lut {
529 /*
530 * Data is U0.16 fixed point format.
531 */
532 __u16 red;
533 __u16 green;
534 __u16 blue;
535 __u16 reserved;
536};
537
456#define DRM_MODE_PAGE_FLIP_EVENT 0x01 538#define DRM_MODE_PAGE_FLIP_EVENT 0x01
457#define DRM_MODE_PAGE_FLIP_ASYNC 0x02 539#define DRM_MODE_PAGE_FLIP_ASYNC 0x02
458#define DRM_MODE_PAGE_FLIP_FLAGS (DRM_MODE_PAGE_FLIP_EVENT|DRM_MODE_PAGE_FLIP_ASYNC) 540#define DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4
541#define DRM_MODE_PAGE_FLIP_TARGET_RELATIVE 0x8
542#define DRM_MODE_PAGE_FLIP_TARGET (DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE | \
543 DRM_MODE_PAGE_FLIP_TARGET_RELATIVE)
544#define DRM_MODE_PAGE_FLIP_FLAGS (DRM_MODE_PAGE_FLIP_EVENT | \
545 DRM_MODE_PAGE_FLIP_ASYNC | \
546 DRM_MODE_PAGE_FLIP_TARGET)
459 547
460/* 548/*
461 * Request a page flip on the specified crtc. 549 * Request a page flip on the specified crtc.
@@ -469,14 +557,16 @@ struct drm_mode_crtc_lut {
469 * flip is already pending as the ioctl is called, EBUSY will be 557 * flip is already pending as the ioctl is called, EBUSY will be
470 * returned. 558 * returned.
471 * 559 *
472 * The ioctl supports one flag, DRM_MODE_PAGE_FLIP_EVENT, which will 560 * Flag DRM_MODE_PAGE_FLIP_EVENT requests that drm sends back a vblank
473 * request that drm sends back a vblank event (see drm.h: struct 561 * event (see drm.h: struct drm_event_vblank) when the page flip is
474 * drm_event_vblank) when the page flip is done. The user_data field 562 * done. The user_data field passed in with this ioctl will be
475 * passed in with this ioctl will be returned as the user_data field 563 * returned as the user_data field in the vblank event struct.
476 * in the vblank event struct.
477 * 564 *
478 * The reserved field must be zero until we figure out something 565 * Flag DRM_MODE_PAGE_FLIP_ASYNC requests that the flip happen
479 * clever to use it for. 566 * 'as soon as possible', meaning that it not delay waiting for vblank.
567 * This may cause tearing on the screen.
568 *
569 * The reserved field must be zero.
480 */ 570 */
481 571
482struct drm_mode_crtc_page_flip { 572struct drm_mode_crtc_page_flip {
@@ -487,29 +577,57 @@ struct drm_mode_crtc_page_flip {
487 __u64 user_data; 577 __u64 user_data;
488}; 578};
489 579
580/*
581 * Request a page flip on the specified crtc.
582 *
583 * Same as struct drm_mode_crtc_page_flip, but supports new flags and
584 * re-purposes the reserved field:
585 *
586 * The sequence field must be zero unless either of the
587 * DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE/RELATIVE flags is specified. When
588 * the ABSOLUTE flag is specified, the sequence field denotes the absolute
589 * vblank sequence when the flip should take effect. When the RELATIVE
590 * flag is specified, the sequence field denotes the relative (to the
591 * current one when the ioctl is called) vblank sequence when the flip
592 * should take effect. NOTE: DRM_IOCTL_WAIT_VBLANK must still be used to
593 * make sure the vblank sequence before the target one has passed before
594 * calling this ioctl. The purpose of the
595 * DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE/RELATIVE flags is merely to clarify
596 * the target for when code dealing with a page flip runs during a
597 * vertical blank period.
598 */
599
600struct drm_mode_crtc_page_flip_target {
601 __u32 crtc_id;
602 __u32 fb_id;
603 __u32 flags;
604 __u32 sequence;
605 __u64 user_data;
606};
607
490/* create a dumb scanout buffer */ 608/* create a dumb scanout buffer */
491struct drm_mode_create_dumb { 609struct drm_mode_create_dumb {
492 __u32 height; 610 __u32 height;
493 __u32 width; 611 __u32 width;
494 __u32 bpp; 612 __u32 bpp;
495 __u32 flags; 613 __u32 flags;
496 /* handle, pitch, size will be returned */ 614 /* handle, pitch, size will be returned */
497 __u32 handle; 615 __u32 handle;
498 __u32 pitch; 616 __u32 pitch;
499 __u64 size; 617 __u64 size;
500}; 618};
501 619
502/* set up for mmap of a dumb scanout buffer */ 620/* set up for mmap of a dumb scanout buffer */
503struct drm_mode_map_dumb { 621struct drm_mode_map_dumb {
504 /** Handle for the object being mapped. */ 622 /** Handle for the object being mapped. */
505 __u32 handle; 623 __u32 handle;
506 __u32 pad; 624 __u32 pad;
507 /** 625 /**
508 * Fake offset to use for subsequent mmap call 626 * Fake offset to use for subsequent mmap call
509 * 627 *
510 * This is a fixed-size type for 32/64 compatibility. 628 * This is a fixed-size type for 32/64 compatibility.
511 */ 629 */
512 __u64 offset; 630 __u64 offset;
513}; 631};
514 632
515struct drm_mode_destroy_dumb { 633struct drm_mode_destroy_dumb {
@@ -517,9 +635,16 @@ struct drm_mode_destroy_dumb {
517}; 635};
518 636
519/* page-flip flags are valid, plus: */ 637/* page-flip flags are valid, plus: */
520#define DRM_MODE_ATOMIC_TEST_ONLY 0x0100 638#define DRM_MODE_ATOMIC_TEST_ONLY 0x0100
521#define DRM_MODE_ATOMIC_NONBLOCK 0x0200 639#define DRM_MODE_ATOMIC_NONBLOCK 0x0200
522#define DRM_MODE_ATOMIC_ALLOW_MODESET 0x0400 640#define DRM_MODE_ATOMIC_ALLOW_MODESET 0x0400
641
642#define DRM_MODE_ATOMIC_FLAGS (\
643 DRM_MODE_PAGE_FLIP_EVENT |\
644 DRM_MODE_PAGE_FLIP_ASYNC |\
645 DRM_MODE_ATOMIC_TEST_ONLY |\
646 DRM_MODE_ATOMIC_NONBLOCK |\
647 DRM_MODE_ATOMIC_ALLOW_MODESET)
523 648
524struct drm_mode_atomic { 649struct drm_mode_atomic {
525 __u32 flags; 650 __u32 flags;
@@ -552,5 +677,8 @@ struct drm_mode_destroy_blob {
552 __u32 blob_id; 677 __u32 blob_id;
553}; 678};
554 679
680#if defined(__cplusplus)
681}
682#endif
555 683
556#endif 684#endif
diff --git a/src/static_libs/libdrm/i915_drm.h b/src/static_libs/libdrm/i915_drm.h
index 0e51d42..5ebe046 100644
--- a/src/static_libs/libdrm/i915_drm.h
+++ b/src/static_libs/libdrm/i915_drm.h
@@ -29,6 +29,10 @@
29 29
30#include "drm.h" 30#include "drm.h"
31 31
32#if defined(__cplusplus)
33extern "C" {
34#endif
35
32/* Please note that modifications to all structs defined here are 36/* Please note that modifications to all structs defined here are
33 * subject to backwards-compatibility constraints. 37 * subject to backwards-compatibility constraints.
34 */ 38 */
@@ -58,6 +62,30 @@
58#define I915_ERROR_UEVENT "ERROR" 62#define I915_ERROR_UEVENT "ERROR"
59#define I915_RESET_UEVENT "RESET" 63#define I915_RESET_UEVENT "RESET"
60 64
65/*
66 * MOCS indexes used for GPU surfaces, defining the cacheability of the
67 * surface data and the coherency for this data wrt. CPU vs. GPU accesses.
68 */
69enum i915_mocs_table_index {
70 /*
71 * Not cached anywhere, coherency between CPU and GPU accesses is
72 * guaranteed.
73 */
74 I915_MOCS_UNCACHED,
75 /*
76 * Cacheability and coherency controlled by the kernel automatically
77 * based on the DRM_I915_GEM_SET_CACHING IOCTL setting and the current
78 * usage of the surface (used for display scanout or not).
79 */
80 I915_MOCS_PTE,
81 /*
82 * Cached in all GPU caches available on the platform.
83 * Coherency between CPU and GPU accesses to the surface is not
84 * guaranteed without extra synchronization.
85 */
86 I915_MOCS_CACHED,
87};
88
61/* Each region is a minimum of 16k, and there are at most 255 of them. 89/* Each region is a minimum of 16k, and there are at most 255 of them.
62 */ 90 */
63#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use 91#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
@@ -218,6 +246,7 @@ typedef struct _drm_i915_sarea {
218#define DRM_I915_OVERLAY_PUT_IMAGE 0x27 246#define DRM_I915_OVERLAY_PUT_IMAGE 0x27
219#define DRM_I915_OVERLAY_ATTRS 0x28 247#define DRM_I915_OVERLAY_ATTRS 0x28
220#define DRM_I915_GEM_EXECBUFFER2 0x29 248#define DRM_I915_GEM_EXECBUFFER2 0x29
249#define DRM_I915_GEM_EXECBUFFER2_WR DRM_I915_GEM_EXECBUFFER2
221#define DRM_I915_GET_SPRITE_COLORKEY 0x2a 250#define DRM_I915_GET_SPRITE_COLORKEY 0x2a
222#define DRM_I915_SET_SPRITE_COLORKEY 0x2b 251#define DRM_I915_SET_SPRITE_COLORKEY 0x2b
223#define DRM_I915_GEM_WAIT 0x2c 252#define DRM_I915_GEM_WAIT 0x2c
@@ -230,6 +259,7 @@ typedef struct _drm_i915_sarea {
230#define DRM_I915_GEM_USERPTR 0x33 259#define DRM_I915_GEM_USERPTR 0x33
231#define DRM_I915_GEM_CONTEXT_GETPARAM 0x34 260#define DRM_I915_GEM_CONTEXT_GETPARAM 0x34
232#define DRM_I915_GEM_CONTEXT_SETPARAM 0x35 261#define DRM_I915_GEM_CONTEXT_SETPARAM 0x35
262#define DRM_I915_PERF_OPEN 0x36
233 263
234#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 264#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
235#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 265#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
@@ -251,6 +281,7 @@ typedef struct _drm_i915_sarea {
251#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) 281#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
252#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) 282#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
253#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) 283#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
284#define DRM_IOCTL_I915_GEM_EXECBUFFER2_WR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2_WR, struct drm_i915_gem_execbuffer2)
254#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 285#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
255#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 286#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
256#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 287#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
@@ -283,6 +314,7 @@ typedef struct _drm_i915_sarea {
283#define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr) 314#define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr)
284#define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param) 315#define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param)
285#define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param) 316#define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param)
317#define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param)
286 318
287/* Allow drivers to submit batchbuffers directly to hardware, relying 319/* Allow drivers to submit batchbuffers directly to hardware, relying
288 * on the security mechanisms provided by hardware. 320 * on the security mechanisms provided by hardware.
@@ -357,6 +389,28 @@ typedef struct drm_i915_irq_wait {
357#define I915_PARAM_HAS_GPU_RESET 35 389#define I915_PARAM_HAS_GPU_RESET 35
358#define I915_PARAM_HAS_RESOURCE_STREAMER 36 390#define I915_PARAM_HAS_RESOURCE_STREAMER 36
359#define I915_PARAM_HAS_EXEC_SOFTPIN 37 391#define I915_PARAM_HAS_EXEC_SOFTPIN 37
392#define I915_PARAM_HAS_POOLED_EU 38
393#define I915_PARAM_MIN_EU_IN_POOL 39
394#define I915_PARAM_MMAP_GTT_VERSION 40
395
396/* Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution
397 * priorities and the driver will attempt to execute batches in priority order.
398 */
399#define I915_PARAM_HAS_SCHEDULER 41
400#define I915_PARAM_HUC_STATUS 42
401
402/* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to opt-out of
403 * synchronisation with implicit fencing on individual objects.
404 * See EXEC_OBJECT_ASYNC.
405 */
406#define I915_PARAM_HAS_EXEC_ASYNC 43
407
408/* Query whether DRM_I915_GEM_EXECBUFFER2 supports explicit fence support -
409 * both being able to pass in a sync_file fd to wait upon before executing,
410 * and being able to return a new sync_file fd that is signaled when the
411 * current request is complete. See I915_EXEC_FENCE_IN and I915_EXEC_FENCE_OUT.
412 */
413#define I915_PARAM_HAS_EXEC_FENCE 44
360 414
361typedef struct drm_i915_getparam { 415typedef struct drm_i915_getparam {
362 __s32 param; 416 __s32 param;
@@ -692,15 +746,41 @@ struct drm_i915_gem_exec_object2 {
692 */ 746 */
693 __u64 offset; 747 __u64 offset;
694 748
695#define EXEC_OBJECT_NEEDS_FENCE (1<<0) 749#define EXEC_OBJECT_NEEDS_FENCE (1<<0)
696#define EXEC_OBJECT_NEEDS_GTT (1<<1) 750#define EXEC_OBJECT_NEEDS_GTT (1<<1)
697#define EXEC_OBJECT_WRITE (1<<2) 751#define EXEC_OBJECT_WRITE (1<<2)
698#define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3) 752#define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3)
699#define EXEC_OBJECT_PINNED (1<<4) 753#define EXEC_OBJECT_PINNED (1<<4)
700#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_PINNED<<1) 754#define EXEC_OBJECT_PAD_TO_SIZE (1<<5)
755/* The kernel implicitly tracks GPU activity on all GEM objects, and
756 * synchronises operations with outstanding rendering. This includes
757 * rendering on other devices if exported via dma-buf. However, sometimes
758 * this tracking is too coarse and the user knows better. For example,
759 * if the object is split into non-overlapping ranges shared between different
760 * clients or engines (i.e. suballocating objects), the implicit tracking
761 * by kernel assumes that each operation affects the whole object rather
762 * than an individual range, causing needless synchronisation between clients.
763 * The kernel will also forgo any CPU cache flushes prior to rendering from
764 * the object as the client is expected to be also handling such domain
765 * tracking.
766 *
767 * The kernel maintains the implicit tracking in order to manage resources
768 * used by the GPU - this flag only disables the synchronisation prior to
769 * rendering with this object in this execbuf.
770 *
771 * Opting out of implicit synhronisation requires the user to do its own
772 * explicit tracking to avoid rendering corruption. See, for example,
773 * I915_PARAM_HAS_EXEC_FENCE to order execbufs and execute them asynchronously.
774 */
775#define EXEC_OBJECT_ASYNC (1<<6)
776/* All remaining bits are MBZ and RESERVED FOR FUTURE USE */
777#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_ASYNC<<1)
701 __u64 flags; 778 __u64 flags;
702 779
703 __u64 rsvd1; 780 union {
781 __u64 rsvd1;
782 __u64 pad_to_size;
783 };
704 __u64 rsvd2; 784 __u64 rsvd2;
705}; 785};
706 786
@@ -772,17 +852,44 @@ struct drm_i915_gem_execbuffer2 {
772#define I915_EXEC_HANDLE_LUT (1<<12) 852#define I915_EXEC_HANDLE_LUT (1<<12)
773 853
774/** Used for switching BSD rings on the platforms with two BSD rings */ 854/** Used for switching BSD rings on the platforms with two BSD rings */
775#define I915_EXEC_BSD_MASK (3<<13) 855#define I915_EXEC_BSD_SHIFT (13)
776#define I915_EXEC_BSD_DEFAULT (0<<13) /* default ping-pong mode */ 856#define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT)
777#define I915_EXEC_BSD_RING1 (1<<13) 857/* default ping-pong mode */
778#define I915_EXEC_BSD_RING2 (2<<13) 858#define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT)
859#define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT)
860#define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT)
779 861
780/** Tell the kernel that the batchbuffer is processed by 862/** Tell the kernel that the batchbuffer is processed by
781 * the resource streamer. 863 * the resource streamer.
782 */ 864 */
783#define I915_EXEC_RESOURCE_STREAMER (1<<15) 865#define I915_EXEC_RESOURCE_STREAMER (1<<15)
784 866
785#define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_RESOURCE_STREAMER<<1) 867/* Setting I915_EXEC_FENCE_IN implies that lower_32_bits(rsvd2) represent
868 * a sync_file fd to wait upon (in a nonblocking manner) prior to executing
869 * the batch.
870 *
871 * Returns -EINVAL if the sync_file fd cannot be found.
872 */
873#define I915_EXEC_FENCE_IN (1<<16)
874
875/* Setting I915_EXEC_FENCE_OUT causes the ioctl to return a sync_file fd
876 * in the upper_32_bits(rsvd2) upon success. Ownership of the fd is given
877 * to the caller, and it should be close() after use. (The fd is a regular
878 * file descriptor and will be cleaned up on process termination. It holds
879 * a reference to the request, but nothing else.)
880 *
881 * The sync_file fd can be combined with other sync_file and passed either
882 * to execbuf using I915_EXEC_FENCE_IN, to atomic KMS ioctls (so that a flip
883 * will only occur after this request completes), or to other devices.
884 *
885 * Using I915_EXEC_FENCE_OUT requires use of
886 * DRM_IOCTL_I915_GEM_EXECBUFFER2_WR ioctl so that the result is written
887 * back to userspace. Failure to do so will cause the out-fence to always
888 * be reported as zero, and the real fence fd to be leaked.
889 */
890#define I915_EXEC_FENCE_OUT (1<<17)
891
892#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_OUT<<1))
786 893
787#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) 894#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
788#define i915_execbuffer2_set_context_id(eb2, context) \ 895#define i915_execbuffer2_set_context_id(eb2, context) \
@@ -812,10 +919,49 @@ struct drm_i915_gem_busy {
812 /** Handle of the buffer to check for busy */ 919 /** Handle of the buffer to check for busy */
813 __u32 handle; 920 __u32 handle;
814 921
815 /** Return busy status (1 if busy, 0 if idle). 922 /** Return busy status
816 * The high word is used to indicate on which rings the object 923 *
817 * currently resides: 924 * A return of 0 implies that the object is idle (after
818 * 16:31 - busy (r or r/w) rings (16 render, 17 bsd, 18 blt, etc) 925 * having flushed any pending activity), and a non-zero return that
926 * the object is still in-flight on the GPU. (The GPU has not yet
927 * signaled completion for all pending requests that reference the
928 * object.) An object is guaranteed to become idle eventually (so
929 * long as no new GPU commands are executed upon it). Due to the
930 * asynchronous nature of the hardware, an object reported
931 * as busy may become idle before the ioctl is completed.
932 *
933 * Furthermore, if the object is busy, which engine is busy is only
934 * provided as a guide. There are race conditions which prevent the
935 * report of which engines are busy from being always accurate.
936 * However, the converse is not true. If the object is idle, the
937 * result of the ioctl, that all engines are idle, is accurate.
938 *
939 * The returned dword is split into two fields to indicate both
940 * the engines on which the object is being read, and the
941 * engine on which it is currently being written (if any).
942 *
943 * The low word (bits 0:15) indicate if the object is being written
944 * to by any engine (there can only be one, as the GEM implicit
945 * synchronisation rules force writes to be serialised). Only the
946 * engine for the last write is reported.
947 *
948 * The high word (bits 16:31) are a bitmask of which engines are
949 * currently reading from the object. Multiple engines may be
950 * reading from the object simultaneously.
951 *
952 * The value of each engine is the same as specified in the
953 * EXECBUFFER2 ioctl, i.e. I915_EXEC_RENDER, I915_EXEC_BSD etc.
954 * Note I915_EXEC_DEFAULT is a symbolic value and is mapped to
955 * the I915_EXEC_RENDER engine for execution, and so it is never
956 * reported as active itself. Some hardware may have parallel
957 * execution engines, e.g. multiple media engines, which are
958 * mapped to the same identifier in the EXECBUFFER2 ioctl and
959 * so are not separately reported for busyness.
960 *
961 * Caveat emptor:
962 * Only the boolean result of this query is reliable; that is whether
963 * the object is idle or busy. The report of which engines are busy
964 * should be only used as a heuristic.
819 */ 965 */
820 __u32 busy; 966 __u32 busy;
821}; 967};
@@ -864,6 +1010,7 @@ struct drm_i915_gem_caching {
864#define I915_TILING_NONE 0 1010#define I915_TILING_NONE 0
865#define I915_TILING_X 1 1011#define I915_TILING_X 1
866#define I915_TILING_Y 2 1012#define I915_TILING_Y 2
1013#define I915_TILING_LAST I915_TILING_Y
867 1014
868#define I915_BIT_6_SWIZZLE_NONE 0 1015#define I915_BIT_6_SWIZZLE_NONE 0
869#define I915_BIT_6_SWIZZLE_9 1 1016#define I915_BIT_6_SWIZZLE_9 1
@@ -1140,7 +1287,145 @@ struct drm_i915_gem_context_param {
1140#define I915_CONTEXT_PARAM_BAN_PERIOD 0x1 1287#define I915_CONTEXT_PARAM_BAN_PERIOD 0x1
1141#define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2 1288#define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2
1142#define I915_CONTEXT_PARAM_GTT_SIZE 0x3 1289#define I915_CONTEXT_PARAM_GTT_SIZE 0x3
1290#define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4
1291#define I915_CONTEXT_PARAM_BANNABLE 0x5
1143 __u64 value; 1292 __u64 value;
1144}; 1293};
1145 1294
1295enum drm_i915_oa_format {
1296 I915_OA_FORMAT_A13 = 1,
1297 I915_OA_FORMAT_A29,
1298 I915_OA_FORMAT_A13_B8_C8,
1299 I915_OA_FORMAT_B4_C8,
1300 I915_OA_FORMAT_A45_B8_C8,
1301 I915_OA_FORMAT_B4_C8_A16,
1302 I915_OA_FORMAT_C4_B8,
1303
1304 I915_OA_FORMAT_MAX /* non-ABI */
1305};
1306
1307enum drm_i915_perf_property_id {
1308 /**
1309 * Open the stream for a specific context handle (as used with
1310 * execbuffer2). A stream opened for a specific context this way
1311 * won't typically require root privileges.
1312 */
1313 DRM_I915_PERF_PROP_CTX_HANDLE = 1,
1314
1315 /**
1316 * A value of 1 requests the inclusion of raw OA unit reports as
1317 * part of stream samples.
1318 */
1319 DRM_I915_PERF_PROP_SAMPLE_OA,
1320
1321 /**
1322 * The value specifies which set of OA unit metrics should be
1323 * be configured, defining the contents of any OA unit reports.
1324 */
1325 DRM_I915_PERF_PROP_OA_METRICS_SET,
1326
1327 /**
1328 * The value specifies the size and layout of OA unit reports.
1329 */
1330 DRM_I915_PERF_PROP_OA_FORMAT,
1331
1332 /**
1333 * Specifying this property implicitly requests periodic OA unit
1334 * sampling and (at least on Haswell) the sampling frequency is derived
1335 * from this exponent as follows:
1336 *
1337 * 80ns * 2^(period_exponent + 1)
1338 */
1339 DRM_I915_PERF_PROP_OA_EXPONENT,
1340
1341 DRM_I915_PERF_PROP_MAX /* non-ABI */
1342};
1343
1344struct drm_i915_perf_open_param {
1345 __u32 flags;
1346#define I915_PERF_FLAG_FD_CLOEXEC (1<<0)
1347#define I915_PERF_FLAG_FD_NONBLOCK (1<<1)
1348#define I915_PERF_FLAG_DISABLED (1<<2)
1349
1350 /** The number of u64 (id, value) pairs */
1351 __u32 num_properties;
1352
1353 /**
1354 * Pointer to array of u64 (id, value) pairs configuring the stream
1355 * to open.
1356 */
1357 __u64 properties_ptr;
1358};
1359
1360/**
1361 * Enable data capture for a stream that was either opened in a disabled state
1362 * via I915_PERF_FLAG_DISABLED or was later disabled via
1363 * I915_PERF_IOCTL_DISABLE.
1364 *
1365 * It is intended to be cheaper to disable and enable a stream than it may be
1366 * to close and re-open a stream with the same configuration.
1367 *
1368 * It's undefined whether any pending data for the stream will be lost.
1369 */
1370#define I915_PERF_IOCTL_ENABLE _IO('i', 0x0)
1371
1372/**
1373 * Disable data capture for a stream.
1374 *
1375 * It is an error to try and read a stream that is disabled.
1376 */
1377#define I915_PERF_IOCTL_DISABLE _IO('i', 0x1)
1378
1379/**
1380 * Common to all i915 perf records
1381 */
1382struct drm_i915_perf_record_header {
1383 __u32 type;
1384 __u16 pad;
1385 __u16 size;
1386};
1387
1388enum drm_i915_perf_record_type {
1389
1390 /**
1391 * Samples are the work horse record type whose contents are extensible
1392 * and defined when opening an i915 perf stream based on the given
1393 * properties.
1394 *
1395 * Boolean properties following the naming convention
1396 * DRM_I915_PERF_SAMPLE_xyz_PROP request the inclusion of 'xyz' data in
1397 * every sample.
1398 *
1399 * The order of these sample properties given by userspace has no
1400 * affect on the ordering of data within a sample. The order is
1401 * documented here.
1402 *
1403 * struct {
1404 * struct drm_i915_perf_record_header header;
1405 *
1406 * { u32 oa_report[]; } && DRM_I915_PERF_PROP_SAMPLE_OA
1407 * };
1408 */
1409 DRM_I915_PERF_RECORD_SAMPLE = 1,
1410
1411 /*
1412 * Indicates that one or more OA reports were not written by the
1413 * hardware. This can happen for example if an MI_REPORT_PERF_COUNT
1414 * command collides with periodic sampling - which would be more likely
1415 * at higher sampling frequencies.
1416 */
1417 DRM_I915_PERF_RECORD_OA_REPORT_LOST = 2,
1418
1419 /**
1420 * An error occurred that resulted in all pending OA reports being lost.
1421 */
1422 DRM_I915_PERF_RECORD_OA_BUFFER_LOST = 3,
1423
1424 DRM_I915_PERF_RECORD_MAX /* non-ABI */
1425};
1426
1427#if defined(__cplusplus)
1428}
1429#endif
1430
1146#endif /* _I915_DRM_H_ */ 1431#endif /* _I915_DRM_H_ */
diff --git a/src/static_libs/libdrm/intel_bufmgr.h b/src/static_libs/libdrm/intel_bufmgr.h
index a1abbcd..693472a 100644
--- a/src/static_libs/libdrm/intel_bufmgr.h
+++ b/src/static_libs/libdrm/intel_bufmgr.h
@@ -184,6 +184,15 @@ int drm_intel_gem_bo_map_unsynchronized(drm_intel_bo *bo);
184int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo); 184int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo);
185int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo); 185int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo);
186 186
187#define HAVE_DRM_INTEL_GEM_BO_DISABLE_IMPLICIT_SYNC 1
188int drm_intel_bufmgr_gem_can_disable_implicit_sync(drm_intel_bufmgr *bufmgr);
189void drm_intel_gem_bo_disable_implicit_sync(drm_intel_bo *bo);
190void drm_intel_gem_bo_enable_implicit_sync(drm_intel_bo *bo);
191
192void *drm_intel_gem_bo_map__cpu(drm_intel_bo *bo);
193void *drm_intel_gem_bo_map__gtt(drm_intel_bo *bo);
194void *drm_intel_gem_bo_map__wc(drm_intel_bo *bo);
195
187int drm_intel_gem_bo_get_reloc_count(drm_intel_bo *bo); 196int drm_intel_gem_bo_get_reloc_count(drm_intel_bo *bo);
188void drm_intel_gem_bo_clear_relocs(drm_intel_bo *bo, int start); 197void drm_intel_gem_bo_clear_relocs(drm_intel_bo *bo, int start);
189void drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable); 198void drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable);
@@ -208,9 +217,17 @@ int drm_intel_bufmgr_gem_get_devid(drm_intel_bufmgr *bufmgr);
208int drm_intel_gem_bo_wait(drm_intel_bo *bo, int64_t timeout_ns); 217int drm_intel_gem_bo_wait(drm_intel_bo *bo, int64_t timeout_ns);
209 218
210drm_intel_context *drm_intel_gem_context_create(drm_intel_bufmgr *bufmgr); 219drm_intel_context *drm_intel_gem_context_create(drm_intel_bufmgr *bufmgr);
220int drm_intel_gem_context_get_id(drm_intel_context *ctx,
221 uint32_t *ctx_id);
211void drm_intel_gem_context_destroy(drm_intel_context *ctx); 222void drm_intel_gem_context_destroy(drm_intel_context *ctx);
212int drm_intel_gem_bo_context_exec(drm_intel_bo *bo, drm_intel_context *ctx, 223int drm_intel_gem_bo_context_exec(drm_intel_bo *bo, drm_intel_context *ctx,
213 int used, unsigned int flags); 224 int used, unsigned int flags);
225int drm_intel_gem_bo_fence_exec(drm_intel_bo *bo,
226 drm_intel_context *ctx,
227 int used,
228 int in_fence,
229 int *out_fence,
230 unsigned int flags);
214 231
215int drm_intel_bo_gem_export_to_prime(drm_intel_bo *bo, int *prime_fd); 232int drm_intel_bo_gem_export_to_prime(drm_intel_bo *bo, int *prime_fd);
216drm_intel_bo *drm_intel_bo_gem_create_from_prime(drm_intel_bufmgr *bufmgr, 233drm_intel_bo *drm_intel_bo_gem_create_from_prime(drm_intel_bufmgr *bufmgr,
@@ -273,6 +290,9 @@ int drm_intel_get_reset_stats(drm_intel_context *ctx,
273int drm_intel_get_subslice_total(int fd, unsigned int *subslice_total); 290int drm_intel_get_subslice_total(int fd, unsigned int *subslice_total);
274int drm_intel_get_eu_total(int fd, unsigned int *eu_total); 291int drm_intel_get_eu_total(int fd, unsigned int *eu_total);
275 292
293int drm_intel_get_pooled_eu(int fd);
294int drm_intel_get_min_eu_in_pool(int fd);
295
276/** @{ Compatibility defines to keep old code building despite the symbol rename 296/** @{ Compatibility defines to keep old code building despite the symbol rename
277 * from dri_* to drm_intel_* 297 * from dri_* to drm_intel_*
278 */ 298 */