forked from enlightenment/efl
evas_cpu: Avoid SIGILL in evas startup on x86
Summary: To determine if a system supports SIMD instructions, the cpuid facility should be used. However, for 15+ years EFL has been trapping SIGILL, then attempting to execute these intstructions. Continuing after SIGILL is explicitly undefined behaviour and can never safely be relied upon - it is possible the CPU will respond to the unknown instruction in an upredictable way and the program will not continue correctly. Even if it hasn't caused problems before, there's no reason to believe a processor released in the future won't behave differently. Lately we've had a couple of bug tickets where SIGILL appears to cause problems at a system level as well, but there seems little point in chasing those problems down as we shouldn't even be doing this in the first place. ref T6711 ref T6989 We still rely on SIGILL in a few configurations where eina_cpu doesn't know how to query features properly (powerpc, sparc, and non linux ARM configurations). Hopefully someone with expertise on those platforms can follow up and we can remove this entirely. Note: MMX2 appears to not really be a thing, and is instead provided by both 3DNow! and SSE. We already conflate it with SSE in other parts of evas, so I've just used SSE here to test for its presence. Depends on D6313 Reviewers: devilhorns, zmike Reviewed By: zmike Subscribers: cedric, #committers, zmike Tags: #efl Maniphest Tasks: T6989, T6711 Differential Revision: https://phab.enlightenment.org/D6314
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@ -1,15 +1,9 @@
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#include "evas_common_private.h"
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#ifdef BUILD_MMX
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#include "evas_mmx.h"
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#endif
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#ifdef BUILD_NEON
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#ifdef BUILD_NEON_INTRINSICS
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#include <arm_neon.h>
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#endif
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#endif
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#if defined BUILD_SSE3
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#include <immintrin.h>
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#endif
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#if defined (HAVE_STRUCT_SIGACTION) && defined (HAVE_SIGLONGJMP)
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#include <signal.h>
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@ -38,46 +32,6 @@ evas_common_cpu_catch_segv(int sig EINA_UNUSED)
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}
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#endif
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void
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evas_common_cpu_mmx_test(void)
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{
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#ifdef BUILD_MMX
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pxor_r2r(mm4, mm4);
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#endif
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}
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void
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evas_common_cpu_mmx2_test(void)
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{
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#ifdef BUILD_MMX
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char data[16];
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data[0] = 0;
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mmx_r2m(movntq, mm0, data);
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data[0] = 0;
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#endif
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}
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void
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evas_common_cpu_sse_test(void)
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{
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#ifdef BUILD_MMX
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int blah[16];
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movntq_r2m(mm0, blah);
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#endif
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}
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void evas_common_op_sse3_test(void);
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void
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evas_common_cpu_sse3_test(void)
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{
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#ifdef BUILD_SSE3
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evas_common_op_sse3_test();
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#endif
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}
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#ifdef BUILD_ALTIVEC
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void
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evas_common_cpu_altivec_test(void)
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@ -181,36 +135,20 @@ evas_common_cpu_init(void)
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if (getenv("EVAS_CPU_NO_MMX"))
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cpu_feature_mask &= ~CPU_FEATURE_MMX;
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else
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{
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cpu_feature_mask |= CPU_FEATURE_MMX *
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evas_common_cpu_feature_test(evas_common_cpu_mmx_test);
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evas_common_cpu_end_opt();
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}
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cpu_feature_mask |= _cpu_check(EINA_CPU_MMX) * CPU_FEATURE_MMX;
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if (getenv("EVAS_CPU_NO_MMX2"))
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cpu_feature_mask &= ~CPU_FEATURE_MMX2;
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else
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{
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cpu_feature_mask |= CPU_FEATURE_MMX2 *
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evas_common_cpu_feature_test(evas_common_cpu_mmx2_test);
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evas_common_cpu_end_opt();
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}
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else /* It seems "MMX2" is actually part of SSE (and 3DNow)? */
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cpu_feature_mask |= _cpu_check(EINA_CPU_SSE) * CPU_FEATURE_MMX2;
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if (getenv("EVAS_CPU_NO_SSE"))
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cpu_feature_mask &= ~CPU_FEATURE_SSE;
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else
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{
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cpu_feature_mask |= CPU_FEATURE_SSE *
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evas_common_cpu_feature_test(evas_common_cpu_sse_test);
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evas_common_cpu_end_opt();
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}
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cpu_feature_mask |= _cpu_check(EINA_CPU_SSE) * CPU_FEATURE_SSE;
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# ifdef BUILD_SSE3
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if (getenv("EVAS_CPU_NO_SSE3"))
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cpu_feature_mask &= ~CPU_FEATURE_SSE3;
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cpu_feature_mask &= ~CPU_FEATURE_SSE3;
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else
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{
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cpu_feature_mask |= CPU_FEATURE_SSE3 *
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evas_common_cpu_feature_test(evas_common_cpu_sse3_test);
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evas_common_cpu_end_opt();
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}
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cpu_feature_mask |= _cpu_check(EINA_CPU_SSE3) * CPU_FEATURE_SSE3;
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# endif /* BUILD_SSE3 */
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#endif /* BUILD_MMX */
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#ifdef BUILD_ALTIVEC
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