739 lines
24 KiB
C
739 lines
24 KiB
C
/* mmx.h
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MultiMedia eXtensions GCC interface library for IA32.
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To use this library, simply include this header file
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and compile with GCC. You MUST have inlining enabled
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in order for mmx_ok() to work; this can be done by
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simply using -O on the GCC command line.
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Compiling with -DMMX_TRACE will cause detailed trace
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output to be sent to stderr for each mmx operation.
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This adds lots of code, and obviously slows execution to
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a crawl, but can be very useful for debugging.
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THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
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EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT
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LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY
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AND FITNESS FOR ANY PARTICULAR PURPOSE.
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1997-98 by H. Dietz and R. Fisher
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History:
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97-98* R.Fisher Early versions
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980501 R.Fisher Original Release
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980611* H.Dietz Rewrite, correctly implementing inlines, and
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R.Fisher including direct register accesses.
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980616 R.Fisher Release of 980611 as 980616.
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980714 R.Fisher Minor corrections to Makefile, etc.
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980715 R.Fisher mmx_ok() now prevents optimizer from using
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clobbered values.
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mmx_ok() now checks if cpuid instruction is
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available before trying to use it.
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980726* R.Fisher mm_support() searches for AMD 3DNow, Cyrix
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Extended MMX, and standard MMX. It returns a
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value which is positive if any of these are
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supported, and can be masked with constants to
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see which. mmx_ok() is now a call to this
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980726* R.Fisher Added i2r support for shift functions
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980919 R.Fisher Fixed AMD extended feature recognition bug.
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980921 R.Fisher Added definition/check for _MMX_H.
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Added "float s[2]" to mmx_t for use with
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3DNow and EMMX. So same mmx_t can be used.
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981013 R.Fisher Fixed cpuid function 1 bug (looked at wrong reg)
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Fixed psllq_i2r error in mmxtest.c
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* Unreleased (internal or interim) versions
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Notes:
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It appears that the latest gas has the pand problem fixed, therefore
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I'll undefine BROKEN_PAND by default.
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String compares may be quicker than the multiple test/jumps in vendor
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test sequence in mmx_ok(), but I'm not concerned with that right now.
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Acknowledgments:
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Jussi Laako for pointing out the errors ultimately found to be
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connected to the failure to notify the optimizer of clobbered values.
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Roger Hardiman for reminding us that CPUID isn't everywhere, and that
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someone may actually try to use this on a machine without CPUID.
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Also for suggesting code for checking this.
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Robert Dale for pointing out the AMD recognition bug.
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Jimmy Mayfield and Carl Witty for pointing out the Intel recognition
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bug.
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Carl Witty for pointing out the psllq_i2r test bug.
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*/
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#ifndef _MMX_H
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#define _MMX_H
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/* Warning: at this writing, the version of GAS packaged
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with most Linux distributions does not handle the
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parallel AND operation mnemonic correctly. If the
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symbol BROKEN_PAND is defined, a slower alternative
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coding will be used. If execution of mmxtest results
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in an illegal instruction fault, define this symbol.
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*/
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#undef BROKEN_PAND
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/* The type of an value that fits in an MMX register
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(note that long long constant values MUST be suffixed
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by LL and unsigned long long values by ULL, lest
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they be truncated by the compiler)
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*/
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typedef union {
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long long q; /* Quadword (64-bit) value */
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unsigned long long uq; /* Unsigned Quadword */
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int d[2]; /* 2 Doubleword (32-bit) values */
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unsigned int ud[2]; /* 2 Unsigned Doubleword */
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short w[4]; /* 4 Word (16-bit) values */
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unsigned short uw[4]; /* 4 Unsigned Word */
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char b[8]; /* 8 Byte (8-bit) values */
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unsigned char ub[8]; /* 8 Unsigned Byte */
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float s[2]; /* Single-precision (32-bit) value */
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} __attribute__ ((aligned (8))) mmx_t;
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/* Helper functions for the instruction macros that follow...
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(note that memory-to-register, m2r, instructions are nearly
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as efficient as register-to-register, r2r, instructions;
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however, memory-to-memory instructions are really simulated
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as a convenience, and are only 1/3 as efficient)
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*/
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/* These macros are a lot simpler without the tracing...
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*/
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#define mmx_i2r(op, imm, reg) \
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__asm__ __volatile__ (#op " $" #imm ", %%" #reg \
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: /* nothing */ \
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: /* nothing */);
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#define mmx_m2r(op, mem, reg) \
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__asm__ __volatile__ (#op " %0, %%" #reg \
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: /* nothing */ \
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: "m" (mem))
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#define mmx_r2m(op, reg, mem) \
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__asm__ __volatile__ (#op " %%" #reg ", %0" \
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: "=m" (mem) \
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: /* nothing */ )
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#define mmx_a2r(op, mem, reg) \
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__asm__ __volatile__ (#op " %0, %%" #reg \
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: /* nothing */ \
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: "m" (mem))
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#define mmx_r2a(op, reg, mem) \
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__asm__ __volatile__ (#op " %%" #reg ", %0" \
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: "=m" (mem) \
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: /* nothing */ )
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#define mmx_r2r(op, regs, regd) \
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__asm__ __volatile__ (#op " %" #regs ", %" #regd)
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#define mmx_m2m(op, mems, memd) \
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__asm__ __volatile__ ("movq %0, %%mm0\n\t" \
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#op " %1, %%mm0\n\t" \
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"movq %%mm0, %0" \
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: "=X" (memd) \
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: "X" (mems))
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/* 1x64 MOVE Quadword
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(this is both a load and a store...
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in fact, it is the only way to store)
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*/
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#define movq_m2r(var, reg) mmx_m2r(movq, var, reg)
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#define movq_r2m(reg, var) mmx_r2m(movq, reg, var)
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#define movq_r2r(regs, regd) mmx_r2r(movq, regs, regd)
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#define movq(vars, vard) \
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__asm__ __volatile__ ("movq %1, %%mm0\n\t" \
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"movq %%mm0, %0" \
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: "=X" (vard) \
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: "X" (vars))
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#define movntq_r2m(reg, var) mmx_r2m(movntq, reg, var)
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/* 1x32 MOVE Doubleword
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(like movq, this is both load and store...
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but is most useful for moving things between
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mmx registers and ordinary registers)
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*/
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#define movd_m2r(var, reg) mmx_a2r(movd, var, reg)
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#define movd_r2m(reg, var) mmx_r2a(movd, reg, var)
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#define movd_r2r(regs, regd) mmx_r2r(movd, regs, regd)
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#define movd(vars, vard) \
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__asm__ __volatile__ ("movd %1, %%mm0\n\t" \
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"movd %%mm0, %0" \
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: "=X" (vard) \
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: "X" (vars))
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/* 2x32, 4x16, and 8x8 Parallel ADDs
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*/
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#define paddd_m2r(var, reg) mmx_m2r(paddd, var, reg)
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#define paddd_r2r(regs, regd) mmx_r2r(paddd, regs, regd)
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#define paddd(vars, vard) mmx_m2m(paddd, vars, vard)
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#define paddw_m2r(var, reg) mmx_m2r(paddw, var, reg)
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#define paddw_r2r(regs, regd) mmx_r2r(paddw, regs, regd)
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#define paddw(vars, vard) mmx_m2m(paddw, vars, vard)
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#define paddb_m2r(var, reg) mmx_m2r(paddb, var, reg)
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#define paddb_r2r(regs, regd) mmx_r2r(paddb, regs, regd)
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#define paddb(vars, vard) mmx_m2m(paddb, vars, vard)
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/* 4x16 and 8x8 Parallel ADDs using Saturation arithmetic
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*/
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#define paddsw_m2r(var, reg) mmx_m2r(paddsw, var, reg)
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#define paddsw_r2r(regs, regd) mmx_r2r(paddsw, regs, regd)
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#define paddsw(vars, vard) mmx_m2m(paddsw, vars, vard)
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#define paddsb_m2r(var, reg) mmx_m2r(paddsb, var, reg)
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#define paddsb_r2r(regs, regd) mmx_r2r(paddsb, regs, regd)
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#define paddsb(vars, vard) mmx_m2m(paddsb, vars, vard)
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/* 4x16 and 8x8 Parallel ADDs using Unsigned Saturation arithmetic
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*/
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#define paddusw_m2r(var, reg) mmx_m2r(paddusw, var, reg)
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#define paddusw_r2r(regs, regd) mmx_r2r(paddusw, regs, regd)
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#define paddusw(vars, vard) mmx_m2m(paddusw, vars, vard)
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#define paddusb_m2r(var, reg) mmx_m2r(paddusb, var, reg)
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#define paddusb_r2r(regs, regd) mmx_r2r(paddusb, regs, regd)
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#define paddusb(vars, vard) mmx_m2m(paddusb, vars, vard)
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/* 2x32, 4x16, and 8x8 Parallel SUBs
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*/
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#define psubd_m2r(var, reg) mmx_m2r(psubd, var, reg)
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#define psubd_r2r(regs, regd) mmx_r2r(psubd, regs, regd)
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#define psubd(vars, vard) mmx_m2m(psubd, vars, vard)
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#define psubw_m2r(var, reg) mmx_m2r(psubw, var, reg)
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#define psubw_r2r(regs, regd) mmx_r2r(psubw, regs, regd)
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#define psubw(vars, vard) mmx_m2m(psubw, vars, vard)
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#define psubb_m2r(var, reg) mmx_m2r(psubb, var, reg)
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#define psubb_r2r(regs, regd) mmx_r2r(psubb, regs, regd)
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#define psubb(vars, vard) mmx_m2m(psubb, vars, vard)
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/* 4x16 and 8x8 Parallel SUBs using Saturation arithmetic
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*/
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#define psubsw_m2r(var, reg) mmx_m2r(psubsw, var, reg)
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#define psubsw_r2r(regs, regd) mmx_r2r(psubsw, regs, regd)
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#define psubsw(vars, vard) mmx_m2m(psubsw, vars, vard)
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#define psubsb_m2r(var, reg) mmx_m2r(psubsb, var, reg)
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#define psubsb_r2r(regs, regd) mmx_r2r(psubsb, regs, regd)
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#define psubsb(vars, vard) mmx_m2m(psubsb, vars, vard)
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/* 4x16 and 8x8 Parallel SUBs using Unsigned Saturation arithmetic
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*/
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#define psubusw_m2r(var, reg) mmx_m2r(psubusw, var, reg)
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#define psubusw_r2r(regs, regd) mmx_r2r(psubusw, regs, regd)
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#define psubusw(vars, vard) mmx_m2m(psubusw, vars, vard)
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#define psubusb_m2r(var, reg) mmx_m2r(psubusb, var, reg)
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#define psubusb_r2r(regs, regd) mmx_r2r(psubusb, regs, regd)
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#define psubusb(vars, vard) mmx_m2m(psubusb, vars, vard)
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/* 4x16 Parallel MULs giving Low 4x16 portions of results
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*/
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#define pmullw_m2r(var, reg) mmx_m2r(pmullw, var, reg)
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#define pmullw_r2r(regs, regd) mmx_r2r(pmullw, regs, regd)
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#define pmullw(vars, vard) mmx_m2m(pmullw, vars, vard)
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/* 4x16 Parallel MULs giving High 4x16 portions of results
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*/
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#define pmulhw_m2r(var, reg) mmx_m2r(pmulhw, var, reg)
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#define pmulhw_r2r(regs, regd) mmx_r2r(pmulhw, regs, regd)
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#define pmulhw(vars, vard) mmx_m2m(pmulhw, vars, vard)
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/* 4x16->2x32 Parallel Mul-ADD
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(muls like pmullw, then adds adjacent 16-bit fields
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in the multiply result to make the final 2x32 result)
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*/
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#define pmaddwd_m2r(var, reg) mmx_m2r(pmaddwd, var, reg)
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#define pmaddwd_r2r(regs, regd) mmx_r2r(pmaddwd, regs, regd)
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#define pmaddwd(vars, vard) mmx_m2m(pmaddwd, vars, vard)
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/* 1x64 bitwise AND
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*/
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#ifdef BROKEN_PAND
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#define pand_m2r(var, reg) \
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{ \
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mmx_m2r(pandn, (mmx_t) -1LL, reg); \
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mmx_m2r(pandn, var, reg); \
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}
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#define pand_r2r(regs, regd) \
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{ \
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mmx_m2r(pandn, (mmx_t) -1LL, regd); \
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mmx_r2r(pandn, regs, regd) \
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}
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#define pand(vars, vard) \
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{ \
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movq_m2r(vard, mm0); \
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mmx_m2r(pandn, (mmx_t) -1LL, mm0); \
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mmx_m2r(pandn, vars, mm0); \
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movq_r2m(mm0, vard); \
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}
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#else
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#define pand_m2r(var, reg) mmx_m2r(pand, var, reg)
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#define pand_r2r(regs, regd) mmx_r2r(pand, regs, regd)
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#define pand(vars, vard) mmx_m2m(pand, vars, vard)
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#endif
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/* 1x64 bitwise AND with Not the destination
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*/
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#define pandn_m2r(var, reg) mmx_m2r(pandn, var, reg)
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#define pandn_r2r(regs, regd) mmx_r2r(pandn, regs, regd)
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#define pandn(vars, vard) mmx_m2m(pandn, vars, vard)
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/* 1x64 bitwise OR
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*/
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#define por_m2r(var, reg) mmx_m2r(por, var, reg)
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#define por_r2r(regs, regd) mmx_r2r(por, regs, regd)
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#define por(vars, vard) mmx_m2m(por, vars, vard)
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/* 1x64 bitwise eXclusive OR
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*/
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#define pxor_m2r(var, reg) mmx_m2r(pxor, var, reg)
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#define pxor_r2r(regs, regd) mmx_r2r(pxor, regs, regd)
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#define pxor(vars, vard) mmx_m2m(pxor, vars, vard)
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/* 2x32, 4x16, and 8x8 Parallel CoMPare for EQuality
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(resulting fields are either 0 or -1)
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*/
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#define pcmpeqd_m2r(var, reg) mmx_m2r(pcmpeqd, var, reg)
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#define pcmpeqd_r2r(regs, regd) mmx_r2r(pcmpeqd, regs, regd)
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#define pcmpeqd(vars, vard) mmx_m2m(pcmpeqd, vars, vard)
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#define pcmpeqw_m2r(var, reg) mmx_m2r(pcmpeqw, var, reg)
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#define pcmpeqw_r2r(regs, regd) mmx_r2r(pcmpeqw, regs, regd)
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#define pcmpeqw(vars, vard) mmx_m2m(pcmpeqw, vars, vard)
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#define pcmpeqb_m2r(var, reg) mmx_m2r(pcmpeqb, var, reg)
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#define pcmpeqb_r2r(regs, regd) mmx_r2r(pcmpeqb, regs, regd)
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#define pcmpeqb(vars, vard) mmx_m2m(pcmpeqb, vars, vard)
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/* 2x32, 4x16, and 8x8 Parallel CoMPare for Greater Than
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(resulting fields are either 0 or -1)
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*/
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#define pcmpgtd_m2r(var, reg) mmx_m2r(pcmpgtd, var, reg)
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#define pcmpgtd_r2r(regs, regd) mmx_r2r(pcmpgtd, regs, regd)
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#define pcmpgtd(vars, vard) mmx_m2m(pcmpgtd, vars, vard)
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#define pcmpgtw_m2r(var, reg) mmx_m2r(pcmpgtw, var, reg)
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#define pcmpgtw_r2r(regs, regd) mmx_r2r(pcmpgtw, regs, regd)
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#define pcmpgtw(vars, vard) mmx_m2m(pcmpgtw, vars, vard)
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#define pcmpgtb_m2r(var, reg) mmx_m2r(pcmpgtb, var, reg)
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#define pcmpgtb_r2r(regs, regd) mmx_r2r(pcmpgtb, regs, regd)
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#define pcmpgtb(vars, vard) mmx_m2m(pcmpgtb, vars, vard)
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/* 1x64, 2x32, and 4x16 Parallel Shift Left Logical
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*/
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#define psllq_i2r(imm, reg) mmx_i2r(psllq, imm, reg)
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#define psllq_m2r(var, reg) mmx_m2r(psllq, var, reg)
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#define psllq_r2r(regs, regd) mmx_r2r(psllq, regs, regd)
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#define psllq(vars, vard) mmx_m2m(psllq, vars, vard)
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#define pslld_i2r(imm, reg) mmx_i2r(pslld, imm, reg)
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#define pslld_m2r(var, reg) mmx_m2r(pslld, var, reg)
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#define pslld_r2r(regs, regd) mmx_r2r(pslld, regs, regd)
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#define pslld(vars, vard) mmx_m2m(pslld, vars, vard)
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#define psllw_i2r(imm, reg) mmx_i2r(psllw, imm, reg)
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#define psllw_m2r(var, reg) mmx_m2r(psllw, var, reg)
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#define psllw_r2r(regs, regd) mmx_r2r(psllw, regs, regd)
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#define psllw(vars, vard) mmx_m2m(psllw, vars, vard)
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/* 1x64, 2x32, and 4x16 Parallel Shift Right Logical
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*/
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#define psrlq_i2r(imm, reg) mmx_i2r(psrlq, imm, reg)
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#define psrlq_m2r(var, reg) mmx_m2r(psrlq, var, reg)
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#define psrlq_r2r(regs, regd) mmx_r2r(psrlq, regs, regd)
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#define psrlq(vars, vard) mmx_m2m(psrlq, vars, vard)
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#define psrld_i2r(imm, reg) mmx_i2r(psrld, imm, reg)
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#define psrld_m2r(var, reg) mmx_m2r(psrld, var, reg)
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#define psrld_r2r(regs, regd) mmx_r2r(psrld, regs, regd)
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#define psrld(vars, vard) mmx_m2m(psrld, vars, vard)
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#define psrlw_i2r(imm, reg) mmx_i2r(psrlw, imm, reg)
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#define psrlw_m2r(var, reg) mmx_m2r(psrlw, var, reg)
|
|
#define psrlw_r2r(regs, regd) mmx_r2r(psrlw, regs, regd)
|
|
#define psrlw(vars, vard) mmx_m2m(psrlw, vars, vard)
|
|
|
|
|
|
/* 2x32 and 4x16 Parallel Shift Right Arithmetic
|
|
*/
|
|
#define psrad_i2r(imm, reg) mmx_i2r(psrad, imm, reg)
|
|
#define psrad_m2r(var, reg) mmx_m2r(psrad, var, reg)
|
|
#define psrad_r2r(regs, regd) mmx_r2r(psrad, regs, regd)
|
|
#define psrad(vars, vard) mmx_m2m(psrad, vars, vard)
|
|
|
|
#define psraw_i2r(imm, reg) mmx_i2r(psraw, imm, reg)
|
|
#define psraw_m2r(var, reg) mmx_m2r(psraw, var, reg)
|
|
#define psraw_r2r(regs, regd) mmx_r2r(psraw, regs, regd)
|
|
#define psraw(vars, vard) mmx_m2m(psraw, vars, vard)
|
|
|
|
|
|
/* 2x32->4x16 and 4x16->8x8 PACK and Signed Saturate
|
|
(packs source and dest fields into dest in that order)
|
|
*/
|
|
#define packssdw_m2r(var, reg) mmx_m2r(packssdw, var, reg)
|
|
#define packssdw_r2r(regs, regd) mmx_r2r(packssdw, regs, regd)
|
|
#define packssdw(vars, vard) mmx_m2m(packssdw, vars, vard)
|
|
|
|
#define packsswb_m2r(var, reg) mmx_m2r(packsswb, var, reg)
|
|
#define packsswb_r2r(regs, regd) mmx_r2r(packsswb, regs, regd)
|
|
#define packsswb(vars, vard) mmx_m2m(packsswb, vars, vard)
|
|
|
|
|
|
/* 4x16->8x8 PACK and Unsigned Saturate
|
|
(packs source and dest fields into dest in that order)
|
|
*/
|
|
#define packuswb_m2r(var, reg) mmx_m2r(packuswb, var, reg)
|
|
#define packuswb_r2r(regs, regd) mmx_r2r(packuswb, regs, regd)
|
|
#define packuswb(vars, vard) mmx_m2m(packuswb, vars, vard)
|
|
|
|
|
|
/* 2x32->1x64, 4x16->2x32, and 8x8->4x16 UNPaCK Low
|
|
(interleaves low half of dest with low half of source
|
|
as padding in each result field)
|
|
*/
|
|
#define punpckldq_m2r(var, reg) mmx_m2r(punpckldq, var, reg)
|
|
#define punpckldq_r2r(regs, regd) mmx_r2r(punpckldq, regs, regd)
|
|
#define punpckldq(vars, vard) mmx_m2m(punpckldq, vars, vard)
|
|
|
|
#define punpcklwd_m2r(var, reg) mmx_m2r(punpcklwd, var, reg)
|
|
#define punpcklwd_r2r(regs, regd) mmx_r2r(punpcklwd, regs, regd)
|
|
#define punpcklwd(vars, vard) mmx_m2m(punpcklwd, vars, vard)
|
|
|
|
#define punpcklbw_m2r(var, reg) mmx_m2r(punpcklbw, var, reg)
|
|
#define punpcklbw_r2r(regs, regd) mmx_r2r(punpcklbw, regs, regd)
|
|
#define punpcklbw(vars, vard) mmx_m2m(punpcklbw, vars, vard)
|
|
|
|
|
|
/* 2x32->1x64, 4x16->2x32, and 8x8->4x16 UNPaCK High
|
|
(interleaves high half of dest with high half of source
|
|
as padding in each result field)
|
|
*/
|
|
#define punpckhdq_m2r(var, reg) mmx_m2r(punpckhdq, var, reg)
|
|
#define punpckhdq_r2r(regs, regd) mmx_r2r(punpckhdq, regs, regd)
|
|
#define punpckhdq(vars, vard) mmx_m2m(punpckhdq, vars, vard)
|
|
|
|
#define punpckhwd_m2r(var, reg) mmx_m2r(punpckhwd, var, reg)
|
|
#define punpckhwd_r2r(regs, regd) mmx_r2r(punpckhwd, regs, regd)
|
|
#define punpckhwd(vars, vard) mmx_m2m(punpckhwd, vars, vard)
|
|
|
|
#define punpckhbw_m2r(var, reg) mmx_m2r(punpckhbw, var, reg)
|
|
#define punpckhbw_r2r(regs, regd) mmx_r2r(punpckhbw, regs, regd)
|
|
#define punpckhbw(vars, vard) mmx_m2m(punpckhbw, vars, vard)
|
|
|
|
#define MOVE_8DWORDS_MMX(src,dst) \
|
|
__asm__ ( \
|
|
"movq (%1), %%mm0 \n" \
|
|
"movq 0x8(%1), %%mm1 \n" \
|
|
"movq 0x10(%1), %%mm2 \n" \
|
|
"movq 0x18(%1), %%mm3 \n" \
|
|
"movq %%mm0, (%0) \n" \
|
|
"movq %%mm1, 0x8(%0) \n" \
|
|
"movq %%mm2, 0x10(%0) \n" \
|
|
"movq %%mm3, 0x18(%0) \n" \
|
|
: \
|
|
: "q" (dst), "r" (src) \
|
|
: "memory", "st");
|
|
|
|
#define MOVE_10DWORDS_MMX(src,dst) \
|
|
__asm__ ( \
|
|
"movq (%1), %%mm0 \n" \
|
|
"movq 0x8(%1), %%mm1 \n" \
|
|
"movq 0x10(%1), %%mm2 \n" \
|
|
"movq 0x18(%1), %%mm3 \n" \
|
|
"movq 0x20(%1), %%mm4 \n" \
|
|
"movq %%mm0, (%0) \n" \
|
|
"movq %%mm1, 0x8(%0) \n" \
|
|
"movq %%mm2, 0x10(%0) \n" \
|
|
"movq %%mm3, 0x18(%0) \n" \
|
|
"movq %%mm4, 0x20(%0) \n" \
|
|
: \
|
|
: "q" (dst), "r" (src) \
|
|
: "memory", "st");
|
|
|
|
#define MOVE_16DWORDS_MMX(src,dst) \
|
|
__asm__ ( \
|
|
"movq (%1), %%mm0 \n" \
|
|
"movq 0x8(%1), %%mm1 \n" \
|
|
"movq 0x10(%1), %%mm2 \n" \
|
|
"movq 0x18(%1), %%mm3 \n" \
|
|
"movq 0x20(%1), %%mm4 \n" \
|
|
"movq 0x28(%1), %%mm5 \n" \
|
|
"movq 0x30(%1), %%mm6 \n" \
|
|
"movq 0x38(%1), %%mm7 \n" \
|
|
"movq %%mm0, (%0) \n" \
|
|
"movq %%mm1, 0x8(%0) \n" \
|
|
"movq %%mm2, 0x10(%0) \n" \
|
|
"movq %%mm3, 0x18(%0) \n" \
|
|
"movq %%mm4, 0x20(%0) \n" \
|
|
"movq %%mm5, 0x28(%0) \n" \
|
|
"movq %%mm6, 0x30(%0) \n" \
|
|
"movq %%mm7, 0x38(%0) \n" \
|
|
: \
|
|
: "q" (dst), "r" (src) \
|
|
: "memory", "st");
|
|
|
|
#define MOVE_16DWORDS_MMX2(src,dst) \
|
|
__asm__ ( \
|
|
"movq (%1), %%mm0 \n" \
|
|
"movq 0x8(%1), %%mm1 \n" \
|
|
"movq 0x10(%1), %%mm2 \n" \
|
|
"movq 0x18(%1), %%mm3 \n" \
|
|
"movq 0x20(%1), %%mm4 \n" \
|
|
"movq 0x28(%1), %%mm5 \n" \
|
|
"movq 0x30(%1), %%mm6 \n" \
|
|
"movq 0x38(%1), %%mm7 \n" \
|
|
"movntq %%mm0, (%0) \n" \
|
|
"movntq %%mm1, 0x8(%0) \n" \
|
|
"movntq %%mm2, 0x10(%0) \n" \
|
|
"movntq %%mm3, 0x18(%0) \n" \
|
|
"movntq %%mm4, 0x20(%0) \n" \
|
|
"movntq %%mm5, 0x28(%0) \n" \
|
|
"movntq %%mm6, 0x30(%0) \n" \
|
|
"movntq %%mm7, 0x38(%0) \n" \
|
|
: \
|
|
: "q" (dst), "r" (src) \
|
|
: "memory", "st");
|
|
|
|
#define MOVE_32DWORDS_SSE2(src,dst) \
|
|
__asm__ ( \
|
|
"movdqu (%1), %%xmm0 \n" \
|
|
"movdqu 0x10(%1), %%xmm1 \n" \
|
|
"movdqu 0x20(%1), %%xmm2 \n" \
|
|
"movdqu 0x30(%1), %%xmm3 \n" \
|
|
"movdqu 0x40(%1), %%xmm4 \n" \
|
|
"movdqu 0x50(%1), %%xmm5 \n" \
|
|
"movdqu 0x60(%1), %%xmm6 \n" \
|
|
"movdqu 0x70(%1), %%xmm7 \n" \
|
|
"movntdq %%xmm0, (%0) \n" \
|
|
"movntdq %%xmm1, 0x10(%0) \n" \
|
|
"movntdq %%xmm2, 0x20(%0) \n" \
|
|
"movntdq %%xmm3, 0x30(%0) \n" \
|
|
"movntdq %%xmm4, 0x40(%0) \n" \
|
|
"movntdq %%xmm5, 0x50(%0) \n" \
|
|
"movntdq %%xmm6, 0x60(%0) \n" \
|
|
"movntdq %%xmm7, 0x70(%0) \n" \
|
|
: \
|
|
: "q" (dst), "r" (src) \
|
|
: "memory", "st");
|
|
|
|
#define MOVE_32DWORDS_ALIGNED_SSE2(src,dst) \
|
|
__asm__ ( \
|
|
"movdqa (%1), %%xmm0 \n" \
|
|
"movdqa 0x10(%1), %%xmm1 \n" \
|
|
"movdqa 0x20(%1), %%xmm2 \n" \
|
|
"movdqa 0x30(%1), %%xmm3 \n" \
|
|
"movdqa 0x40(%1), %%xmm4 \n" \
|
|
"movdqa 0x50(%1), %%xmm5 \n" \
|
|
"movdqa 0x60(%1), %%xmm6 \n" \
|
|
"movdqa 0x70(%1), %%xmm7 \n" \
|
|
"movntdq %%xmm0, (%0) \n" \
|
|
"movntdq %%xmm1, 0x10(%0) \n" \
|
|
"movntdq %%xmm2, 0x20(%0) \n" \
|
|
"movntdq %%xmm3, 0x30(%0) \n" \
|
|
"movntdq %%xmm4, 0x40(%0) \n" \
|
|
"movntdq %%xmm5, 0x50(%0) \n" \
|
|
"movntdq %%xmm6, 0x60(%0) \n" \
|
|
"movntdq %%xmm7, 0x70(%0) \n" \
|
|
: \
|
|
: "q" (dst), "r" (src) \
|
|
: "memory", "st");
|
|
|
|
/* Empty MMx State
|
|
(used to clean-up when going from mmx to float use
|
|
of the registers that are shared by both; note that
|
|
there is no float-to-mmx operation needed, because
|
|
only the float tag word info is corruptible)
|
|
*/
|
|
|
|
#define emms() __asm__ __volatile__ ("emms":::"memory")
|
|
#define sfence() __asm__ __volatile__ ("sfence":::"memory")
|
|
|
|
/* additions to detect mmx - */
|
|
/* Raster <raster@rasterman.com> */
|
|
|
|
#ifndef CPUID_MMX
|
|
# define CPUID_MMX (1 << 23) /* flags: mmx */
|
|
#endif
|
|
#ifndef CPUID_SSE
|
|
# define CPUID_SSE (1 << 25) /* flags: xmm */
|
|
#endif
|
|
#ifndef CPUID_SSE2
|
|
# define CPUID_SSE2 (1 << 26) /* flags: ? */
|
|
#endif
|
|
|
|
#ifdef __amd64
|
|
#define have_cpuid(cpuid_ret) \
|
|
__asm__ __volatile__ ( \
|
|
".align 32 \n" \
|
|
" pushq %%rbx \n" \
|
|
" pushfq \n" \
|
|
" popq %%rax \n" \
|
|
" movq %%rax, %%rbx \n" \
|
|
" xorq $0x200000, %%rax \n" \
|
|
" pushq %%rax \n" \
|
|
" popfq \n" \
|
|
" pushfq \n" \
|
|
" popq %%rax \n" \
|
|
" cmpq %%rax, %%rbx \n" \
|
|
" je 1f \n" \
|
|
" movl $1, %0 \n" \
|
|
" jmp 2f \n" \
|
|
"1: \n" \
|
|
" movl $0, %0 \n" \
|
|
"2: \n" \
|
|
" popq %%rbx \n" \
|
|
: "=m" (cpuid_ret) \
|
|
);
|
|
|
|
#define get_cpuid(cpuid_ret) \
|
|
__asm__ __volatile__ ( \
|
|
".align 32 \n" \
|
|
" pushq %%rax \n" \
|
|
" movl $1, %%eax \n" \
|
|
" cpuid \n" \
|
|
" test $0x00800000, %%edx\n" \
|
|
"1: \n" \
|
|
" movl %%edx, %0 \n" \
|
|
" jmp 2f \n" \
|
|
"2: \n" \
|
|
" movl $0, %0 \n" \
|
|
" popq %%rax \n" \
|
|
: "=m" (cpuid_ret) \
|
|
);
|
|
#else
|
|
#define have_cpuid(cpuid_ret) \
|
|
__asm__ __volatile__ ( \
|
|
".align 32 \n" \
|
|
" pushl %%ebx \n" \
|
|
" pushfl \n" \
|
|
" popl %%eax \n" \
|
|
" movl %%eax, %%ebx \n" \
|
|
" xorl $0x200000, %%eax \n" \
|
|
" pushl %%eax \n" \
|
|
" popfl \n" \
|
|
" pushfl \n" \
|
|
" popl %%eax \n" \
|
|
" cmpl %%eax, %%ebx \n" \
|
|
" je 1f \n" \
|
|
" movl $1, %0 \n" \
|
|
" jmp 2f \n" \
|
|
"1: \n" \
|
|
" movl $0, %0 \n" \
|
|
"2: \n" \
|
|
" popl %%ebx \n" \
|
|
: "=m" (cpuid_ret) \
|
|
);
|
|
|
|
#define get_cpuid(cpuid_ret) \
|
|
__asm__ __volatile__ ( \
|
|
".align 32 \n" \
|
|
" pushl %%eax \n" \
|
|
" movl $1, %%eax \n" \
|
|
" cpuid \n" \
|
|
" test $0x00800000, %%edx\n" \
|
|
"1: \n" \
|
|
" movl %%edx, %0 \n" \
|
|
" jmp 2f \n" \
|
|
"2: \n" \
|
|
" movl $0, %0 \n" \
|
|
" popl %%eax \n" \
|
|
: "=m" (cpuid_ret) \
|
|
);
|
|
#endif
|
|
#define prefetch(var) \
|
|
__asm__ __volatile__ ( \
|
|
"prefetchnta (%0) \n" \
|
|
: \
|
|
: "r" (var) \
|
|
);
|
|
#define prefetch0(var) \
|
|
__asm__ __volatile__ ( \
|
|
"prefetcht0 (%0) \n" \
|
|
: \
|
|
: "r" (var) \
|
|
);
|
|
#define prefetch1(var) \
|
|
__asm__ __volatile__ ( \
|
|
"prefetcht1 (%0) \n" \
|
|
: \
|
|
: "r" (var) \
|
|
);
|
|
#define prefetch2(var) \
|
|
__asm__ __volatile__ ( \
|
|
"prefetcht2 (%0) \n" \
|
|
: \
|
|
: "r" (var) \
|
|
);
|
|
#define pshufw(r1, r2, imm) \
|
|
__asm__ __volatile__ ( \
|
|
"pshufw $" #imm ", %" #r1 ", %" #r2 " \n" \
|
|
);
|
|
|
|
#define pshufhw(r1, r2, imm) \
|
|
__asm__ __volatile__ ( \
|
|
"pshufhw $" #imm ", %" #r1 ", %" #r2 " \n" \
|
|
);
|
|
|
|
#define pshuflw(r1, r2, imm) \
|
|
__asm__ __volatile__ ( \
|
|
"pshuflw $" #imm ", %" #r1 ", %" #r2 " \n" \
|
|
);
|
|
#define pshufd(r1, r2, imm) \
|
|
__asm__ __volatile__ ( \
|
|
"pshufd $" #imm ", %" #r1 ", %" #r2 " \n" \
|
|
);
|
|
|
|
/* 1x238 MOVE Doouble Quadword
|
|
(this is both a load and a store...
|
|
in fact, it is the only way to store)
|
|
*/
|
|
#define movdqu_m2r(var, reg) mmx_m2r(movdqu, var, reg)
|
|
#define movdqu_r2m(reg, var) mmx_r2m(movdqu, reg, var)
|
|
#define movdqu_r2r(regs, regd) mmx_r2r(movdqu, regs, regd)
|
|
#define movdqu(vars, vard) \
|
|
__asm__ __volatile__ ("movdqu %1, %%xmm0\n\t" \
|
|
"movdqu %%xmm0, %0" \
|
|
: "=X" (vard) \
|
|
: "X" (vars))
|
|
#define movdqa_m2r(var, reg) mmx_m2r(movdqa, var, reg)
|
|
#define movdqa_r2m(reg, var) mmx_r2m(movdqa, reg, var)
|
|
#define movdqa_r2r(regs, regd) mmx_r2r(movdqa, regs, regd)
|
|
#define movdqa(vars, vard) \
|
|
__asm__ __volatile__ ("movdqa %1, %%xmm0\n\t" \
|
|
"movdqa %%xmm0, %0" \
|
|
: "=X" (vard) \
|
|
: "X" (vars))
|
|
#define movntdq_r2m(reg, var) mmx_r2m(movntdq, reg, var)
|
|
|
|
|
|
/* end additions */
|
|
|
|
#endif
|