forked from enlightenment/efl
494 lines
16 KiB
C
494 lines
16 KiB
C
#define NEONDEBUG 0
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#if NEONDEBUG
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#define DEBUG_FNCOUNT(x) \
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do { \
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static int _foo = 0; \
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if (_foo++%10000 ==0) \
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printf("%s %+d %s: %d (%s)\n",__FILE__,__LINE__,__FUNCTION__,\
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_foo, x " optimised");\
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} while (0)
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#else
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#define DEBUG_FNCOUNT(x) ((void)x)
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#endif
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/* blend mask x color -> dst */
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#ifdef BUILD_NEON
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static void
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_op_blend_mas_c_dp_neon(DATA32 *s EINA_UNUSED, DATA8 *m, DATA32 c, DATA32 *d, int l) {
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// main loop process data in pairs, so we need count to be even
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DATA32 *e = d + l - (l % 2);
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// everything we can do only once per cycle
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// loading of 'c', initialization of some registers
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__asm__ __volatile__
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(
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".fpu neon \n\t"
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" vmov.32 d30[0], %[c] \n\t"
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" vmov.i16 q10, #255 \n\t"
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" vmov.i16 q11, #256 \n\t"
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" veor d29, d29, d29 \n\t"
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" vzip.8 d30, d29 \n\t"
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" vmov d31, d30 \n\t"
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:
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: [c] "r" (c)
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: "q10", "q11", "q15", "d29"
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);
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while (d < e)
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{
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// main cycle
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__asm__ __volatile__
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(
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// load pair '*d' and '*(d+1)' into vector register
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" vldm %[d], {d4} \n\t"
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// load '*m' and '*(m+1)'
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" veor q0, q0, q0 \n\t"
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" vld1.8 d0[0], [%[m]]! \n\t"
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" vld1.8 d1[0], [%[m]]! \n\t"
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// spread values from d in vector registers so for each
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// 8 bit channel data we have 8 bit of zeros
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// so each 32bit value occupies now one 64 bit register
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" veor d5, d5, d5 \n\t"
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" vzip.8 d4, d5 \n\t"
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// copy *m values in corresponding registers
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" vdup.u16 d0, d0[0] \n\t"
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" vdup.u16 d1, d1[0] \n\t"
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// multiply a * c
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" vmul.u16 q13, q0, q15 \n\t"
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" vadd.i16 q13, q13, q10 \n\t"
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" vsri.16 q13, q13, #8 \n\t"
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" vand q13, q13, q10 \n\t"
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// extract negated alpha
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" vdup.u16 d24, d26[3] \n\t"
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" vdup.u16 d25, d27[3] \n\t"
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" vsub.i16 q12, q11, q12 \n\t"
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// multiply alpha * (*d) and add a*c
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" vmul.u16 q2, q2, q12 \n\t"
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" vsri.16 q2, q2, #8 \n\t"
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" vand q2, q2, q10 \n\t"
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" vadd.i16 q2, q2, q13 \n\t"
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" vand q2, q2, q10 \n\t"
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// save results
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" vqmovn.u16 d4, q2 \n\t"
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" vstm %[d]!, {d4} \n\t"
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: [d] "+r" (d), [m] "+r" (m)
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: [c] "r" (c)
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: "q0", "q2", "q15", "q13", "q12", "q11", "q10",
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"memory"
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);
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}
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if (l % 2)
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{
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// do analogue of main loop for last element, if needed
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__asm__ __volatile__
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(
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" vld1.32 d4[0], [%[d]] \n\t"
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" veor d0, d0, d0 \n\t"
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" vld1.8 d0[0], [%[m]]! \n\t"
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" veor d5, d5, d5 \n\t"
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" vzip.8 d4, d5 \n\t"
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" vdup.u16 d0, d0[0] \n\t"
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" vmul.u16 d26, d0, d30 \n\t"
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" vadd.i16 d26, d26, d20 \n\t"
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" vsri.16 d26, d26, #8 \n\t"
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" vand d26, d26, d20 \n\t"
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" vdup.u16 d24, d26[3] \n\t"
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" vsub.i16 d24, d22, d24 \n\t"
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" vmul.u16 d4, d4, d24 \n\t"
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" vsri.16 d4, d4, #8 \n\t"
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" vand d4, d4, d20 \n\t"
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" vadd.i16 d4, d4, d26 \n\t"
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" vand d4, d4, d20 \n\t"
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" vqmovn.u16 d4, q2 \n\t"
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" vst1.32 {d4[0]}, [%[d]]! \n\t"
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: [d] "+r" (d), [m] "+r" (m)
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: [c] "r" (c)
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: "q0", "q2", "q15", "q13", "q12", "q11", "q10",
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"memory"
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);
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}
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}
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#endif
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#ifdef BUILD_NEON
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static void
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_op_blend_mas_can_dp_neon(DATA32 *s EINA_UNUSED, DATA8 *m, DATA32 c, DATA32 *d, int l) {
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DATA32 *e,*tmp;
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int alpha;
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DEBUG_FNCOUNT("");
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#define AP "_blend_mas_can_dp_neon_"
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asm volatile (
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".fpu neon \n\t"
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"vdup.u32 q9, %[c] \n\t"
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"vmov.i8 q15, #1 \n\t"
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"vmov.i8 q14, #0 \n\t"
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// Make C 16 bit (C in q3/q2)
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"vmovl.u8 q3, d19 \n\t"
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"vmovl.u8 q2, d18 \n\t"
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// Which loop to start
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" andS %[tmp], %[d],$0xf \n\t"
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" beq "AP"quadloop \n\t"
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" andS %[tmp], %[d], #4 \n\t"
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" beq "AP"dualstart \n\t"
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AP"singleloop: \n\t"
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" vld1.8 d0[0], [%[m]]! \n\t"
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" vld1.32 d8[0], [%[d]] \n\t"
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" vdup.u8 d0, d0[0] \n\t"
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" vshr.u8 d0, d0, #1 \n\t"
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" vmovl.u8 q0, d0 \n\t"
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" vmovl.u8 q4, d8 \n\t"
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" vsub.s16 q6, q2, q4 \n\t"
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" vmul.s16 q6, q0 \n\t"
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" vshr.s16 q6, #7 \n\t"
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" vadd.s16 q6, q4 \n\t"
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" vqmovun.s16 d2, q6 \n\t"
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" vst1.32 d2[0], [%[d]]! \n\t"
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" andS %[tmp], %[d], $0xf \n\t"
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" beq "AP"quadloop \n\t"
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AP"dualstart: \n\t"
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" sub %[tmp], %[e], %[d] \n\t"
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" cmp %[tmp], #16 \n\t"
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" blt "AP"loopout \n\t"
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AP"dualloop: \n\t"
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" vld1.16 d0[0], [%[m]]! \n\t"
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" vldm %[d], {d8} \n\t"
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" vmovl.u8 q0, d0 \n\t"
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" vmovl.u8 q0, d0 \n\t"
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" vmul.u32 d0, d0, d30 \n\t"
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" vshr.u8 d0, d0, #1 \n\t"
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" vmovl.u8 q0, d0 \n\t"
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" vmovl.u8 q4, d8 \n\t"
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" vsub.s16 q6, q2, q4 \n\t"
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" vmul.s16 q6, q0 \n\t"
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" vshr.s16 q6, #7 \n\t"
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" vadd.s16 q6, q4 \n\t"
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" vqmovun.s16 d2, q6 \n\t"
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" vstm %[d]!, {d2} \n\t"
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AP"quadloop: \n\t"
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" sub %[tmp], %[e], %[d] \n\t"
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" cmp %[tmp], #16 \n\t"
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" blt "AP"loopout \n\t"
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" sub %[tmp], %[e], #15 \n\t"
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" sub %[d], #16 \n\t"
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AP"fastloop: \n\t"
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" add %[d], #16 \n\t"
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" cmp %[tmp], %[d] \n\t"
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" blt "AP"loopout \n\t"
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AP"quadloopint: \n\t"
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// Load the mask: 4 bytes: It has d0/d1
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" ldr %[x], [%[m]] \n\t"
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" add %[m], #4 \n\t"
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// Check for shortcuts
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" cmp %[x], #0 \n\t"
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" beq "AP"fastloop \n\t"
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" cmp %[x], $0xffffffff \n\t"
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" beq "AP"quadstore \n\t"
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" vmov.32 d0[0], %[x] \n\t"
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// Load d into d8/d9 q4
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" vldm %[d], {d8,d9} \n\t"
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// Get the alpha channel ready (m)
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" vmovl.u8 q0, d0 \n\t"
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" vmovl.u8 q0, d0 \n\t"
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" vmul.u32 q0, q0,q15 \n\t"
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// Lop a bit off to prevent overflow
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" vshr.u8 q0, q0, #1 \n\t"
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// Now make it 16 bit
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" vmovl.u8 q1, d1 \n\t"
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" vmovl.u8 q0, d0 \n\t"
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// 16 bit 'd'
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" vmovl.u8 q5, d9 \n\t"
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" vmovl.u8 q4, d8 \n\t"
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// Diff 'd' & 'c'
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" vsub.s16 q7, q3, q5 \n\t"
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" vsub.s16 q6, q2, q4 \n\t"
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" vmul.s16 q7, q1 \n\t"
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" vmul.s16 q6, q0 \n\t"
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// Shift results a bit
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" vshr.s16 q7, #7 \n\t"
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" vshr.s16 q6, #7 \n\t"
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// Add 'd'
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" vadd.s16 q7, q5 \n\t"
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" vadd.s16 q6, q4 \n\t"
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// Make sure none are negative
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" vqmovun.s16 d9, q7 \n\t"
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" vqmovun.s16 d8, q6 \n\t"
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" vstm %[d]!, {d8,d9} \n\t"
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" cmp %[tmp], %[d] \n\t"
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" bhi "AP"quadloopint \n\t"
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" b "AP"loopout \n\t"
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AP"quadstore: \n\t"
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" vstm %[d]!, {d18,d19} \n\t"
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" cmp %[tmp], %[d] \n\t"
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" bhi "AP"quadloopint \n\t"
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AP"loopout: \n\t"
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#if NEONDEBUG
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"cmp %[d], %[e] \n\t"
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"ble "AP"foo \n\t"
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"sub %[tmp], %[tmp] \n\t"
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"vst1.32 d0[0], [%[tmp]] \n\t"
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AP"foo: \n\t"
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#endif
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" cmp %[e], %[d] \n\t"
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" beq "AP"done \n\t"
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" sub %[tmp],%[e], %[d] \n\t"
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" cmp %[tmp],#8 \n\t"
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" blt "AP"onebyte \n\t"
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// Load the mask: 2 bytes: It has d0
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" vld1.16 d0[0], [%[m]]! \n\t"
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// Load d into d8/d9 q4
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" vldm %[d], {d8} \n\t"
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// Get the alpha channel ready (m)
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" vmovl.u8 q0, d0 \n\t"
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" vmovl.u8 q0, d0 \n\t"
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" vmul.u32 d0, d0, d30 \n\t"
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// Lop a bit off to prevent overflow
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" vshr.u8 d0, d0, #1 \n\t"
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// Now make it 16 bit
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" vmovl.u8 q0, d0 \n\t"
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// 16 bit 'd'
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" vmovl.u8 q4, d8 \n\t"
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// Diff 'd' & 'c'
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" vsub.s16 q6, q2, q4 \n\t"
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" vmul.s16 q6, q0 \n\t"
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// Shift results a bit
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" vshr.s16 q6, #7 \n\t"
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// Add 'd'
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"vadd.s16 q6, q4 \n\t"
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// Make sure none are negative
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"vqmovun.s16 d2, q6 \n\t"
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"vstm %[d]!, {d2} \n\t"
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"cmp %[e], %[d] \n\t"
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"beq "AP"done \n\t"
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AP"onebyte: \n\t"
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"vld1.8 d0[0], [%[m]]! \n\t"
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"vld1.32 d8[0], [%[d]] \n\t"
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"vdup.u8 d0, d0[0] \n\t"
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"vshr.u8 d0, d0, #1 \n\t"
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"vmovl.u8 q0, d0 \n\t"
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"vmovl.u8 q4, d8 \n\t"
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"vsub.s16 q6, q2, q4 \n\t"
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"vmul.s16 q6, q0 \n\t"
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"vshr.s16 q6, #7 \n\t"
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"vadd.s16 q6, q4 \n\t"
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"vqmovun.s16 d2, q6 \n\t"
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"vst1.32 d2[0], [%[d]]! \n\t"
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AP"done: \n\t"
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#if NEONDEBUG
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"cmp %[d], %[e] \n\t"
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"beq "AP"reallydone \n\t"
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"sub %[m], %[m] \n\t"
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"vst1.32 d0[0], [%[m]] \n\t"
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AP"reallydone:"
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#endif
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: // output regs
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// Input
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: [e] "r" (e = d + l), [d] "r" (d), [c] "r" (c),
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[m] "r" (m), [tmp] "r" (7), [x] "r" (33)
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: "q0", "q1", "q2","q3", "q4","q5","q6", "q7","q9","q14","q15",
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"memory" // clobbered
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);
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#undef AP
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}
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#endif
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#ifdef BUILD_NEON
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#define _op_blend_mas_cn_dp_neon _op_blend_mas_can_dp_neon
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#define _op_blend_mas_caa_dp_neon _op_blend_mas_c_dp_neon
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#define _op_blend_mas_c_dpan_neon _op_blend_mas_c_dp_neon
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#define _op_blend_mas_cn_dpan_neon _op_blend_mas_cn_dp_neon
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#define _op_blend_mas_can_dpan_neon _op_blend_mas_can_dp_neon
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#define _op_blend_mas_caa_dpan_neon _op_blend_mas_caa_dp_neon
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static void
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init_blend_mask_color_span_funcs_neon(void)
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{
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op_blend_span_funcs[SP_N][SM_AS][SC][DP][CPU_NEON] = _op_blend_mas_c_dp_neon;
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op_blend_span_funcs[SP_N][SM_AS][SC_N][DP][CPU_NEON] = _op_blend_mas_cn_dp_neon;
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op_blend_span_funcs[SP_N][SM_AS][SC_AN][DP][CPU_NEON] = _op_blend_mas_can_dp_neon;
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op_blend_span_funcs[SP_N][SM_AS][SC_AA][DP][CPU_NEON] = _op_blend_mas_caa_dp_neon;
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op_blend_span_funcs[SP_N][SM_AS][SC][DP_AN][CPU_NEON] = _op_blend_mas_c_dpan_neon;
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op_blend_span_funcs[SP_N][SM_AS][SC_N][DP_AN][CPU_NEON] = _op_blend_mas_cn_dpan_neon;
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op_blend_span_funcs[SP_N][SM_AS][SC_AN][DP_AN][CPU_NEON] = _op_blend_mas_can_dpan_neon;
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op_blend_span_funcs[SP_N][SM_AS][SC_AA][DP_AN][CPU_NEON] = _op_blend_mas_caa_dpan_neon;
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}
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#endif
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#ifdef BUILD_NEON
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static void
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_op_blend_pt_mas_c_dp_neon(DATA32 s, DATA8 m, DATA32 c, DATA32 *d) {
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s = MUL_SYM(m, c);
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c = 256 - (s >> 24);
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*d = MUL_SYM(*d >> 24, s) + MUL_256(c, *d);
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}
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#define _op_blend_pt_mas_cn_dp_neon _op_blend_pt_mas_c_dp_neon
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#define _op_blend_pt_mas_can_dp_neon _op_blend_pt_mas_c_dp_neon
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#define _op_blend_pt_mas_caa_dp_neon _op_blend_pt_mas_c_dp_neon
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#define _op_blend_pt_mas_c_dpan_neon _op_blend_pt_mas_c_dp_neon
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#define _op_blend_pt_mas_cn_dpan_neon _op_blend_pt_mas_cn_dp_neon
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#define _op_blend_pt_mas_can_dpan_neon _op_blend_pt_mas_can_dp_neon
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#define _op_blend_pt_mas_caa_dpan_neon _op_blend_pt_mas_caa_dp_neon
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static void
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init_blend_mask_color_pt_funcs_neon(void)
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{
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op_blend_pt_funcs[SP_N][SM_AS][SC][DP][CPU_NEON] = _op_blend_pt_mas_c_dp_neon;
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op_blend_pt_funcs[SP_N][SM_AS][SC_N][DP][CPU_NEON] = _op_blend_pt_mas_cn_dp_neon;
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op_blend_pt_funcs[SP_N][SM_AS][SC_AN][DP][CPU_NEON] = _op_blend_pt_mas_can_dp_neon;
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op_blend_pt_funcs[SP_N][SM_AS][SC_AA][DP][CPU_NEON] = _op_blend_pt_mas_caa_dp_neon;
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op_blend_pt_funcs[SP_N][SM_AS][SC][DP_AN][CPU_NEON] = _op_blend_pt_mas_c_dpan_neon;
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op_blend_pt_funcs[SP_N][SM_AS][SC_N][DP_AN][CPU_NEON] = _op_blend_pt_mas_cn_dpan_neon;
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op_blend_pt_funcs[SP_N][SM_AS][SC_AN][DP_AN][CPU_NEON] = _op_blend_pt_mas_can_dpan_neon;
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op_blend_pt_funcs[SP_N][SM_AS][SC_AA][DP_AN][CPU_NEON] = _op_blend_pt_mas_caa_dpan_neon;
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}
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#endif
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/*-----*/
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/* blend_rel mask x color -> dst */
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#ifdef BUILD_NEON
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static void
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_op_blend_rel_mas_c_dp_neon(DATA32 *s EINA_UNUSED, DATA8 *m, DATA32 c, DATA32 *d, int l) {
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DATA32 *e;
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int alpha;
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DEBUG_FNCOUNT("not");
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UNROLL8_PLD_WHILE(d, l, e,
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{
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DATA32 mc = MUL_SYM(*m, c);
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alpha = 256 - (mc >> 24);
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*d = MUL_SYM(*d >> 24, mc) + MUL_256(alpha, *d);
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d++;
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m++;
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});
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}
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#define _op_blend_rel_mas_cn_dp_neon _op_blend_rel_mas_c_dp_neon
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#define _op_blend_rel_mas_can_dp_neon _op_blend_rel_mas_c_dp_neon
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#define _op_blend_rel_mas_caa_dp_neon _op_blend_rel_mas_c_dp_neon
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#define _op_blend_rel_mas_c_dpan_neon _op_blend_mas_c_dpan_neon
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#define _op_blend_rel_mas_cn_dpan_neon _op_blend_mas_cn_dpan_neon
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#define _op_blend_rel_mas_can_dpan_neon _op_blend_mas_can_dpan_neon
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#define _op_blend_rel_mas_caa_dpan_neon _op_blend_mas_caa_dpan_neon
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static void
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init_blend_rel_mask_color_span_funcs_neon(void)
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{
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op_blend_rel_span_funcs[SP_N][SM_AS][SC][DP][CPU_NEON] = _op_blend_rel_mas_c_dp_neon;
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op_blend_rel_span_funcs[SP_N][SM_AS][SC_N][DP][CPU_NEON] = _op_blend_rel_mas_cn_dp_neon;
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op_blend_rel_span_funcs[SP_N][SM_AS][SC_AN][DP][CPU_NEON] = _op_blend_rel_mas_can_dp_neon;
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op_blend_rel_span_funcs[SP_N][SM_AS][SC_AA][DP][CPU_NEON] = _op_blend_rel_mas_caa_dp_neon;
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op_blend_rel_span_funcs[SP_N][SM_AS][SC][DP_AN][CPU_NEON] = _op_blend_rel_mas_c_dpan_neon;
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op_blend_rel_span_funcs[SP_N][SM_AS][SC_N][DP_AN][CPU_NEON] = _op_blend_rel_mas_cn_dpan_neon;
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op_blend_rel_span_funcs[SP_N][SM_AS][SC_AN][DP_AN][CPU_NEON] = _op_blend_rel_mas_can_dpan_neon;
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op_blend_rel_span_funcs[SP_N][SM_AS][SC_AA][DP_AN][CPU_NEON] = _op_blend_rel_mas_caa_dpan_neon;
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}
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#endif
|
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#ifdef BUILD_NEON
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static void
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_op_blend_rel_pt_mas_c_dp_neon(DATA32 s, DATA8 m, DATA32 c, DATA32 *d) {
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s = MUL_SYM(m, c);
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c = 256 - (s >> 24);
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*d = MUL_SYM(*d >> 24, s) + MUL_256(c, *d);
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}
|
|
|
|
#define _op_blend_rel_pt_mas_cn_dp_neon _op_blend_rel_pt_mas_c_dp_neon
|
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#define _op_blend_rel_pt_mas_can_dp_neon _op_blend_rel_pt_mas_c_dp_neon
|
|
#define _op_blend_rel_pt_mas_caa_dp_neon _op_blend_rel_pt_mas_c_dp_neon
|
|
|
|
#define _op_blend_rel_pt_mas_c_dpan_neon _op_blend_pt_mas_c_dpan_neon
|
|
#define _op_blend_rel_pt_mas_cn_dpan_neon _op_blend_pt_mas_cn_dpan_neon
|
|
#define _op_blend_rel_pt_mas_can_dpan_neon _op_blend_pt_mas_can_dpan_neon
|
|
#define _op_blend_rel_pt_mas_caa_dpan_neon _op_blend_pt_mas_caa_dpan_neon
|
|
|
|
static void
|
|
init_blend_rel_mask_color_pt_funcs_neon(void)
|
|
{
|
|
op_blend_rel_pt_funcs[SP_N][SM_AS][SC][DP][CPU_NEON] = _op_blend_rel_pt_mas_c_dp_neon;
|
|
op_blend_rel_pt_funcs[SP_N][SM_AS][SC_N][DP][CPU_NEON] = _op_blend_rel_pt_mas_cn_dp_neon;
|
|
op_blend_rel_pt_funcs[SP_N][SM_AS][SC_AN][DP][CPU_NEON] = _op_blend_rel_pt_mas_can_dp_neon;
|
|
op_blend_rel_pt_funcs[SP_N][SM_AS][SC_AA][DP][CPU_NEON] = _op_blend_rel_pt_mas_caa_dp_neon;
|
|
|
|
op_blend_rel_pt_funcs[SP_N][SM_AS][SC][DP_AN][CPU_NEON] = _op_blend_rel_pt_mas_c_dpan_neon;
|
|
op_blend_rel_pt_funcs[SP_N][SM_AS][SC_N][DP_AN][CPU_NEON] = _op_blend_rel_pt_mas_cn_dpan_neon;
|
|
op_blend_rel_pt_funcs[SP_N][SM_AS][SC_AN][DP_AN][CPU_NEON] = _op_blend_rel_pt_mas_can_dpan_neon;
|
|
op_blend_rel_pt_funcs[SP_N][SM_AS][SC_AA][DP_AN][CPU_NEON] = _op_blend_rel_pt_mas_caa_dpan_neon;
|
|
}
|
|
#endif
|