forked from enlightenment/efl
eina+evas cpu - add theoretical SVE support
SVE is a new-ish ARM vector instruction set like neon... but with wider vectors (and variable vector sizes). this adds the flags and hwcaps checks.
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@ -49,7 +49,7 @@
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#include "eina_log.h"
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#include "eina_cpu.h"
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#if defined(HAVE_SYS_AUXV_H) && defined(HAVE_ASM_HWCAP_H) && defined(__arm__) && defined(__linux__)
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#if defined(HAVE_SYS_AUXV_H) && defined(HAVE_ASM_HWCAP_H) && (defined(__arm__) || defined(__aarch64__)) && defined(__linux__)
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# include <sys/auxv.h>
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# include <asm/hwcap.h>
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#endif
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@ -126,7 +126,7 @@ void _x86_simd(Eina_Cpu_Features *features)
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}
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#endif
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#if defined(HAVE_SYS_AUXV_H) && defined(HAVE_ASM_HWCAP_H) && defined(__arm__) && defined(__linux__)
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#if defined(HAVE_SYS_AUXV_H) && defined(HAVE_ASM_HWCAP_H) && (defined(__arm__) || defined(__aarch64__)) && defined(__linux__)
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static void
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_arm_cpu_features(Eina_Cpu_Features *features)
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{
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@ -134,8 +134,15 @@ _arm_cpu_features(Eina_Cpu_Features *features)
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aux = getauxval(AT_HWCAP);
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if (aux & HWCAP_NEON)
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# if defined(__aarch64__)
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*features |= EINA_CPU_NEON;
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# endif
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# ifdef HWCAP_NEON
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if (aux & HWCAP_NEON) *features |= EINA_CPU_NEON;
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# endif
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# ifdef HWCAP_SVE
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if (aux & HWCAP_SVE) *features |= EINA_CPU_SVE;
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# endif
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}
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#endif
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@ -157,7 +164,7 @@ eina_cpu_init(void)
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{
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#if defined(__i386__) || defined(__x86_64__)
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_x86_simd(&eina_cpu_features);
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#elif defined(HAVE_SYS_AUXV_H) && defined(HAVE_ASM_HWCAP_H) && defined(__arm__) && defined(__linux__)
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#elif defined(HAVE_SYS_AUXV_H) && defined(HAVE_ASM_HWCAP_H) && (defined(__arm__) || defined(__aarch64__)) && defined(__linux__)
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_arm_cpu_features(&eina_cpu_features);
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#endif
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@ -55,7 +55,8 @@ typedef enum _Eina_Cpu_Features
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EINA_CPU_NEON = 0x00000040,
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EINA_CPU_SSSE3 = 0x00000080,
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EINA_CPU_SSE41 = 0x00000100,
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EINA_CPU_SSE42 = 0x00000200
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EINA_CPU_SSE42 = 0x00000200,
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EINA_CPU_SVE = 0x00000400
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} Eina_Cpu_Features;
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/**
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@ -7,7 +7,6 @@
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static int cpu_feature_mask = 0;
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#ifdef BUILD_ALTIVEC
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# ifdef __POWERPC__
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# ifdef __VEC__
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@ -26,6 +25,12 @@ static int cpu_feature_mask = 0;
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# endif
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#endif
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#if defined(__aarch64__)
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# ifdef BUILD_NEON
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# define NEED_FEATURE_TEST
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# endif
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#endif
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#ifdef NEED_FEATURE_TEST
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# ifdef HAVE_SIGLONGJMP
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# include <signal.h>
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@ -70,6 +75,7 @@ evas_common_cpu_neon_test(void)
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# ifdef BUILD_NEON
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# ifdef BUILD_NEON_INTRINSICS
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volatile uint32x4_t temp = vdupq_n_u32(0x1);
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vaddq_u32(temp, temp);
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# else
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asm volatile (
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".fpu neon \n\t"
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@ -84,6 +90,15 @@ evas_common_cpu_neon_test(void)
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//#endif
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}
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void
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evas_common_cpu_sve_test(void)
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{
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#if defined(__aarch64__)
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volatile int result = 123;
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asm("movz %w[res], #10" : [res] "=r" (result));
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#endif
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}
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void
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evas_common_cpu_vis_test(void)
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{
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@ -164,6 +179,10 @@ evas_common_cpu_feature_test(void (*feature)(void))
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# ifdef BUILD_NEON
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if (feature == evas_common_cpu_neon_test)
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return _cpu_check(EINA_CPU_NEON);
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# endif
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# if defined(__aarch64__)
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if (feature == evas_common_cpu_sve_test)
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return _cpu_check(EINA_CPU_SVE);
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# endif
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return 0;
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# endif
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@ -249,6 +268,23 @@ evas_common_cpu_init(void)
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else
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cpu_feature_mask |= CPU_FEATURE_NEON;
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#endif
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#if defined(__aarch64__)
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if (getenv("EVAS_CPU_NO_SVE"))
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cpu_feature_mask &= ~CPU_FEATURE_SVE;
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else
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{
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# if defined(HAVE_SYS_AUXV_H) && defined(HAVE_ASM_HWCAP_H) && defined(__arm__) && defined(__linux__)
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#error "xx"
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cpu_feature_mask |= CPU_FEATURE_SVE *
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!!(eina_cpu_features_get() & EINA_CPU_SVE);
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# else
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cpu_feature_mask |= CPU_FEATURE_SVE *
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evas_common_cpu_feature_test(evas_common_cpu_sve_test);
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evas_common_cpu_end_opt();
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# endif
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}
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#endif
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}
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int
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@ -503,7 +503,8 @@ typedef enum _CPU_Features
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CPU_FEATURE_VIS = (1 << 4),
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CPU_FEATURE_VIS2 = (1 << 5),
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CPU_FEATURE_NEON = (1 << 6),
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CPU_FEATURE_SSE3 = (1 << 7)
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CPU_FEATURE_SSE3 = (1 << 7),
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CPU_FEATURE_SVE = (1 << 8)
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} CPU_Features;
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/*****************************************************************************/
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